CEG 320/52010: Memory and cache2 The Memory Hierarchy Registers Primary cache Secondary cache Main memory Magnetic disk ~2ns ~4-5ns ~30ns ~220ns+ >1ms (~6ms)
CEG 320/52010: Memory and cache3 Cache & Locality Cache sits between the CPU and main memory –Invisible to the CPU Only useful if recently used items are used again Fortunately, this happens a lot. We call this property locality of reference. CPU Cache Main Memory
CEG 320/52010: Memory and cache4 Locality of reference Temporal locality –Recently accessed data/instructions are likely to be accessed again. Most program time is spent in loops Arrays are often scanned multiple times Spatial locality –If I access memory address n, I am likely to then access another address close to n (usually n+1, n+2, or n+4) Linear execution of code Linear access of arrays
CEG 320/52010: Memory and cache5 How a cache exploits locality Temporal – When an item is accessed from memory it is brought into the cache –If it is accessed again soon, it comes from the cache and not main memory Spatial – When we access a memory word, we also fetch the next few words of memory into the cache –The number of words fetched is the cache line size, or the cache block size for the machine
CEG 320/52010: Memory and cache6 Cache write policies As long as we are only doing READ operations, the cache is an exact copy of a small part of the main memory When we write, should we write to cache or memory? Write through cache – write to both cache and main memory. Cache and memory are always consistent Write back cache – write only to cache and set a dirty bit. When the block gets replaced from the cache, write it out to memory. When might the write-back policy be dangerous?
CEG 320/52010: Memory and cache7 Cache mapping Direct mapped – each memory block can occupy one and only one cache block Example: –Cache block size: 16 words –Memory = 64K (4K blocks) –Cache = 2K (128 blocks)
CEG 320/52010: Memory and cache8 Direct Mapped Cache Memory block n occupies cache block (n mod 128) Consider address $2EF block: $2EF = 751 word: 4 Cache: tag: 5 block: 111 word: 4
CEG 320/52010: Memory and cache9 Fully Associative Cache More efficient cache utilization –No wasted cache space Slower cache search –Must check the tag of every entry in the cache to see if the block we want is there.
CEG 320/52010: Memory and cache10 Set-associative mapping Blocks are grouped into sets Each memory block can occupy any block in its set This example is 2- way set-associative Which of the two blocks do we replace?
CEG 320/52010: Memory and cache11 Replacement algorithms Random Oldest first Least accesses Least recently used (LRU): replace the block that has gone the longest time without being referenced. –This is the most commonly-used replacement algorithm –Easy to implement with a small counter…
CEG 320/52010: Memory and cache12 Implementing LRU replacement Suppose we have a 4-way set associative cache… Block 0 Block 1 Block 2 Block 3 Set Hit: Increment lower counters Reset counter to 00 Miss Replace the 11 Set to 00 Increment all other counters
CEG 320/52010: Memory and cache13 Interactions with DMA If we have a write-back cache, DMA must check the cache before acting. –Many systems simply flush the cache before DMA write operations What if we have a memory word in the cache, and the DMA controller changes that word? –Stale data We keep a valid bit for each cache line. When DMA changes memory, it must also set the valid bit to 0 for that cache line. –Cache coherence
CEG 320/52010: Memory and cache15 Memory Interleaving Memory is organized into modules or banks Within a bank, capacitors must be recharged after each read operation Successive reads to the same bank are slow … 00F8 00FA 00FC 00FE Module … 01F8 01FA 01FC 01FE … 02F8 02FA 02FC 02FE Byte Non-interleaved C 0012 … 02E8 02EE 02F4 02FA Module E 0014 … 02EA 02F0 02F6 02FC A … 02EC 02F2 02F8 02FE Byte Interleaved
CEG 320/52010: Memory and cache16 Measuring Cache Performance No cache: Often about 10 cycles per memory access Simple cache: –t ave = hC + (1-h)M –C is often 1 clock cycle –Assume M is 17 cycles (to load an entire cache line) –Assume h is about 90% –t ave =.9 (1) + (.1)17 = 2.6 cycles/access –What happens when h is 95%?
CEG 320/52010: Memory and cache17 Multi-level cache performance t ave = h 1 C 1 + (1-h 1 ) h 2 C 2 + (1-h 1 ) (1-h 2 ) M –h 1 = hit rate in primary cache –h 2 = hit rate in secondary cache –C 1 = time to access primary cache –C 2 = time to access secondary cache –M = miss penalty (time to load an entire cache line from main memory)
CEG 320/52010: Memory and cache18 Virtual Memory
CEG 320/52010: Memory and cache19 Virtual Memory: Introduction Motorola has 24-bit memory addressing and is byte addressable –Can address 2 24 bytes of memory – 16 MB Intel Pentiums have 32-bit memory addressing and are byte addressable –Can address 2 32 bytes of memory – 4 GB What good is all that address space if you only have 256MB of main memory (RAM)?
CEG 320/52010: Memory and cache20 Virtual Memory: Introduction Unreal Tournament (full install) uses 2.4 gigabytes on your hard disk. You may only have 256 megabytes of RAM (main memory). How can you play the game if you cant fit it all into main memory? Other Examples: –Neverwinter Nights – 2 gigabytes –Microsoft Office – 243 megabytes –Quicken Basic 2000 – 28 megabytes
CEG 320/52010: Memory and cache21 Working Set Not all of a program needs to be in memory while you are executing it: –Error handling routines are not called very often. –Character creation generally only happens at the start of the game… why keep that code easily available? Working set is the memory that is consumed at any moment by a program while it is running. –Includes stack, allocated memory, active instructions, etc. Examples: –Unreal Tournament – 100MB (requires 128MB) –Internet Explorer – 20MB
CEG 320/52010: Memory and cache22 Virtual Memory In modern computers it is possible to use more memory than the amount physically available in the system Memory not currently being used is temporarily stored on magnetic disk Essentially, the main memory acts as a cache for the virtual memory on disk.
CEG 320/52010: Memory and cache23 Memory Management Unit (MMU) Virtual memory must be invisible to the CPU –Appears as one large address space The MMU sits between the CPU and the memory system Translates virtual addresses to real (physical) addresses
CEG 320/52010: Memory and cache24 Paged Memory Memory is divided into pages –Conceptually like a cache block –Typically 2K to 16K in size –A page can live anywhere in main memory, or on the disk Like cache, we need some way of knowing what page is where in memory –Page table instead of tags –Page table base register stores the address of the page table
CEG 320/52010: Memory and cache25 Page lookup in the page table Control bits: –Valid –Modified –Accessed Occasionally cleared by the OS Used for LRU replacement TLB: A cache for the page table
CEG 320/52010: Memory and cache26 The TLB A special, fully- associative cache for the page table is used to speed page lookup This cache is called the Translation Lookaside Buffer or TLB.
CEG 320/52010: Memory and cache27 Page Faults If the memory address desired cannot be found in the TLB, then a page fault has occurred, and the page containing that memory must be loaded from the disk into main memory. Page faults are costly because moving 2K – 16K (page size) can take a while. What if you have too many page faults?
CEG 320/52010: Memory and cache28 Thrashing If a process does not have enough frames to hold its current working set, the page-fault rate is very high Thrashing –a process is thrashing when it spends more time paging than executing –w/ local replacement algorithms, a process may thrash even though memory is available –w/ global replacement algorithms, the entire system may thrash Less thrashing in general, but is it fair?
CEG 320/52010: Memory and cache29 Thrashing Diagram Why does paging work? Locality model –Process migrates from one locality to another. –Localities may overlap. Why does thrashing occur? size of locality > total memory size What should we do? –suspend one or more processes!
CEG 320/52010: Memory and cache30 Program Structure How should we arrange memory references to large arrays? –Is the array stored in row-major or column-major order? Example: –Array A[1024, 1024] of type integer –Page size = 1K Each row is stored in one page –System has one frame –Program 1 for i := 1 to 1024 do for j := 1 to 1024 do A[i,j] := 0; 1024 page faults –Program 2 for j := 1 to 1024 do for i := 1 to 1024 do A[i,j] := 0; 1024 x 1024 page faults