Презентация на тему: " Unit-4 TRANSISTOR CHARACTERISTICS: Junction transistor, Transistor current components, Transistor as an amplifier, Transistor Construction, Detailed study." — Транскрипт:
Unit-4 TRANSISTOR CHARACTERISTICS: Junction transistor, Transistor current components, Transistor as an amplifier, Transistor Construction, Detailed study of currents in a transistor in common Base, Common Emitter, and Common Collector configurations, Relation between Alpha and Beta, Typical Transistor junction voltage values, JFET characteristics ( Qualitative and Quantitative discussion ), small Signal model of JET,MOSFET characteristics( Enhancement and depletion mode), symbols of MOSFET, comparison of transistors, Introduction to SCR and UJT.
Introduction The basic of electronic system nowadays is semiconductor device. The famous and commonly use of this device is BJTs (Bipolar Junction Transistors). It can be use as amplifier and logic switches. BJT consists of three terminal: collector : C base: B emitter : E Two types of BJT : pnp and npn
Transistor Construction 3 layer semiconductor device consisting: –2 n- and 1 p-type layers of material npn transistor –2 p- and 1 n-type layers of material pnp transistor The term bipolar reflects the fact that holes and electrons participate in the injection process into the oppositely polarized material A single pn junction has two different types of bias: – forward bias – reverse bias Thus, a two-pn-junction device has four types of bias.
Position of the terminals and symbol of BJT. Base is located at the middle and more thin from the level of collector and emitter The emitter and collector terminals are made of the same type of semiconductor material, while the base of the other type of material Base is located at the middle and more thin from the level of collector and emitter The emitter and collector terminals are made of the same type of semiconductor material, while the base of the other type of material
Transistor currents -The arrow is always drawn on the emitter -The arrow always point toward the n-type -The arrow indicates the direction of the emitter current: pnp:E B npn: B E I C =the collector current I B = the base current I E = the emitter current
By imaging the analogy of diode, transistor can be construct like two diodes that connetecd together. It can be conclude that the work of transistor is base on work of diode.
Transistor Operation The basic operation will be described using the pnp transistor. The operation of the pnp transistor is exactly the same if the roles played by the electron and hole are interchanged. One p-n junction of a transistor is reverse-biased, whereas the other is forward-biased. Forward-biased junction of a pnp transistor Reverse-biased junction of a pnp transistor
Both biasing potentials have been applied to a pnp transistor and resulting majority and minority carrier flows indicated. Majority carriers (+) will diffuse across the forward- biased p-n junction into the n-type material. A very small number of carriers (+) will through n-type material to the base terminal. Resulting IB is typically in order of microamperes. The large number of majority carriers will diffuse across the reverse-biased junction into the p-type material connected to the collector terminal.
Majority carriers can cross the reverse-biased junction because the injected majority carriers will appear as minority carriers in the n-type material. Applying KCL to the transistor : I E = I C + I B The comprises of two components – the majority and minority carriers I C = I Cmajority + I COminority I CO – I C current with emitter terminal open and is called leakage current.
Common-Base Configuration Common-base terminology is derived from the fact that the : - base is common to both input and output of the configuration. - base is usually the terminal closest to or at ground potential. All current directions will refer to conventional (hole) flow and the arrows in all electronic symbols have a direction defined by this convention. Note that the applied biasing (voltage sources) are such as to establish current in the direction indicated for each branch.
To describe the behavior of common-base amplifiers requires two set of characteristics: -Input or driving point characteristics. -Output or collector characteristics The output characteristics has 3 basic regions: -Active region –defined by the biasing arrangements -Cutoff region – region where the collector current is 0A -Saturation region- region of the characteristics to the left of V CB = 0V
The curves (output characteristics) clearly indicate that a first approximation to the relationship between IE and IC in the active region is given by I C IE Once a transistor is in the on state, the base-emitter voltage will be assumed to be V BE = 0.7V
In the dc mode the level of I C and I E due to the majority carriers are related by a quantity called alpha = I C = I E + I CBO It can then be summarize to I C = I E (ignore I CBO due to small value) For ac situations where the point of operation moves on the characteristics curve, an ac alpha defined by common base current gain factorAlpha a common base current gain factor that shows the efficiency by calculating the current percent from current flow from emitter to collector.The value of is typical from 0.9 ~
Biasing Proper biasing CB configuration in active region by approximation I C I E (I B 0 uA)
Common-Emitter Configuration It is called common-emitter configuration since : - emitter is common or reference to both input and output terminals. - emitter is usually the terminal closest to or at ground potential. due to the high gain for current and voltageAlmost amplifier design is using connection of CE due to the high gain for current and voltage. Two set of characteristics are necessary to describe the behavior for CE ;input (base terminal) and output (collector terminal) parameters.
Proper Biasing common-emitter configuration in active region
Input characteristics for a common-emitter NPN transistor I B is microamperes compared to miliamperes of I C. I B will flow when V BE > 0.7V for silicon and 0.3V for germanium Before this value I B is very small and no I B. Base-emitter junction is forward bias Increasing V CE will reduce I B for different values.
Output characteristics for a common-emitter npn transistor For small V CE (V CE < V CESAT, I C increase linearly with increasing of V CE V CE > V CESAT I C not totally depends on V CE constant I C I B (uA) is very small compare to I C (mA). Small increase in I B cause big increase in I C I B =0 A I CEO occur. Noticing the value when I C =0A. There is still some value of current flows.
Beta () or amplification factor The ratio of dc collector current (IC) to the dc base current (IB) is dc beta (dc ) which is dc current gain where IC and IB are determined at a particular operating point, Q- point (quiescent point). Its define by the following equation: 30 < dc < 300 2N3904 dc =hfehOn data sheet, dc =hfe with h is derived from ac hybrid equivalent cct. FE are derived from forward-current amplification and common-emitter configuration respectively.
For ac conditions an ac beta has been defined as the changes of collector current (I C ) compared to the changes of base current (I B ) where I C and I B are determined at operating point. On data sheet, ac =hfe It can defined by the following equation:
Example From output characteristics of common emitter configuration, find ac and dc with an Operating point at I B =25 A and V CE =7.5V.
Common – Collector Configuration Also called emitter-follower (EF). It is called common-emitter configuration since both the signal source and the load share the collector terminal as a common connection point. The output voltage is obtained at emitter terminal. The input characteristic of common-collector configuration is similar with common-emitter. configuration. Common-collector circuit configuration is provided with the load resistor connected from emitter to ground. It is used primarily for impedance-matching purpose since it has high input impedance and low output impedance.
Notation and symbols used with the common-collector configuration: (a) pnp transistor ; (b) npn transistor.
For the common-collector configuration, the output characteristics are a plot of I E vs V CE for a range of values of I B.
Limits of Operation Many BJT transistor used as an amplifier. Thus it is important to notice the limits of operations. At least 3 maximum values is mentioned in data sheet. There are: a) Maximum power dissipation at collector: P Cmax or P D b) Maximum collector-emitter voltage: V CEmax sometimes named as V BR(CEO ) or V CEO. c) Maximum collector current: ICmax There are few rules that need to be followed for BJT transistor used as an amplifier. The rules are: i) transistor need to be operate in active region! ii) I C < I Cmax ii) P C < P Cmax
Note: V CE is at maximum and I C is at minimum (I CMAX =I CEO ) in the cutoff region. I C is at maximum and V CE is at minimum (V CE max = V cesat = V CEO ) in the saturation region. The transistor operates in the active region between saturation and cutoff.
Refer to the fig. Step1: The maximum collector power dissipation, P D =I CMAX x V CEmax (1) = 18m x 20 = 360 mW Step 2: At any point on the characteristics the product of and must be equal to 360 mW. Ex. 1. If choose I Cmax = 5 mA, substitute into the (1), we get V CEmax I Cmax = 360 mW V CEmax (5 m)=360/5=7.2 V Ex.2. If choose V CEmax =18 V, substitute into (1), we get V CEmax I Cmax = 360 mW (10) I CMAX =360m/18=20 mA
Derating P Dmax P DMAX is usually specified at 25°C. The higher temperature goes, the less is P DMAX Example; –A derating factor of 2mW/°C indicates the power dissipation is reduced 2mW each degree centigrade increase of temperature.
The Field Effect Transistor (FET) In 1945, Shockley had an idea for making a solid state device out of semiconductors. He reasoned that a strong electrical field could cause the flow of electricity within a nearby semiconductor. He tried to build one, but it didn't work. Three years later, Brattain & Bardeen built the first working transistor, the germanium point-contact transistor, which was designed as the junction (sandwich) transistor. In 1960 Bell scientist John Atalla developed a new design based on Shockley's original field-effect theories. By the late 1960s, manufacturers converted from junction type integrated circuits to field effect devices.
Field effect devices are those in which current is controlled by the action of an electron field, rather than carrier injection. Field-effect transistors are so named because a weak electrical signal coming in through one electrode creates an electrical field through the rest of the transistor. The FET was known as a unipolar transistor. The term refers to the fact that current is transported by carriers of one polarity (majority), whereas in the conventional bipolar transistor carriers of both polarities (majority and minority) are involved. The Field Effect Transistor (FET)
The family of FET devices may be divided into : Junction FET Depletion Mode MOSFET Enhancement Mode MOSFET
Junction FETs (JFETs) JFETs consists of a piece of high-resistivity semiconductor material (usually Si) which constitutes a channel for the majority carrier flow. Conducting semiconductor channel between two ohmic contacts – source & drain
Junction FETs JFET is a high-input resistance device, while the BJT is comparatively low. If the channel is doped with a donor impurity, n-type material is formed and the channel current will consist of electrons. If the channel is doped with an acceptor impurity, p- type material will be formed and the channel current will consist of holes. N-channel devices have greater conductivity than p- channel types, since electrons have higher mobility than do holes; thus n-channel JFETs are approximately twice as efficient conductors compared to their p-channel counterparts.
Junction FETs (JFETs) The magnitude of this current is controlled by a voltage applied to a gate, which is a reverse-biased. The fundamental difference between JFET and BJT devices: when the JFET junction is reverse-biased the gate current is practically zero, whereas the base current of the BJT is always some value greater than zero.
Basic structure of JFETs In addition to the channel, a JFET contains two ohmic contacts: the source and the drain. The JFET will conduct current equally well in either direction and the source and drain leads are usually interchangeable.
N-channel JFET This transistor is made by forming a channel of N-type material in a P- type substrate. Three wires are then connected to the device. One at each end of the channel. One connected to the substrate. In a sense, the device is a bit like a PN-junction diode, except that there are two wires connected to the N-type side.
How JFET Function The gate is connected to the source. Since the pn junction is reverse-biased, little current will flow in the gate connection. The potential gradient established will form a depletion layer, where almost all the electrons present in the n-type channel will be swept away. The most depleted portion is in the high field between the G and the D, and the least- depleted area is between the G and the S.
Because the flow of current along the channel from the (+ve) drain to the (-ve) source is really a flow of free electrons from S to D in the n-type Si, the magnitude of this current will fall as more Si becomes depleted of free electrons. There is a limit to the drain current (I D ) which increased V DS can drive through the channel. This limiting current is known as I DSS (Drain-to- Source current with the gate shorted to the source). How JFET Function
The output characteristics of an n-channel JFET with the gate short-circuited to the source. The initial rise in I D is related to the buildup of the depletion layer as V DS increases. The curve approaches the level of the limiting current I DSS when I D begins to be pinched off. The physical meaning of this term leads to one definition of pinch-off voltage, V P, which is the value of V DS at which the maximum I DSS flows.
With a steady gate-source voltage of 1 V there is always 1 V across the wall of the channel at the source end. A drain-source voltage of 1 V means that there will be 2 V across the wall at the drain end. (The drain is up 1V from the source potential and the gate is 1V down, hence the total difference is 2V.) The higher voltage difference at the drain end means that the electron channel is squeezed down a bit more at this end.
When the drain-source voltage is increased to 10V the voltage across the channel walls at the drain end increases to 11V, but remains just 1V at the source end. The field across the walls near the drain end is now a lot larger than at the source end. As a result the channel near the drain is squeezed down quite a lot.
Increasing the source-drain voltage to 20V squeezes down this end of the channel still more. As we increase this voltage we increase the electric field which drives electrons along the open part of the channel. However, also squeezes down the channel near the drain end. This reduction in the open channel width makes it harder for electrons to pass. As a result the drain-source current tends to remain constant when we increase the drain- source voltage.
Increasing V DS increases the widths of depletion layers, which penetrate more into channel and hence result in more channel narrowing toward the drain. The resistance of the n-channel, R AB therefore increases with V DS. The drain current: I DS = V DS /R AB I D versus V DS exhibits a sub linear behavior, see figure for V DS < 5V. The pinch-off voltage, V P is the magnitude of reverse bias needed across the p + n junction to make them just touch at the drain end. Since actual bias voltage across p + n junction at drain end is V GD, the pinch-off occur whenever: V GD = -V P.
Beyond V DS = V P, there is a short pinch-off channel of length, po. As V DS increases, most of additional voltage simply drops across as this region is depleted of carriers and hence highly resistive. Voltage drop across channel length, L ch remain as V P. Beyond pinch-off then I D = V P /R AP (V DS >V P ).
What happen when negative voltage, says V GS = -2V, is applied to gate with respect to source (with V DS =0). The p + n junction are now reverse biased from the start, the channel is narrower, and channel resistance is now larger than in the V GS = 0 case.
The drain current that flows when a small V DS applied (Fig b) is now smaller than in V GS = 0 case. Applied V DS = 3 V to pinch-off the channel (Fig c). When V DS = 3V, V GD across p + n junction at drain end is -5V, which is –V P, so channel becomes pinch-off. Beyond pinch-off, I D is nearly saturated just as in the V GS =0 case. Pinch-off occurs at V DS = V DS(sat), V DS(sat) = V P +V GS, where V GS is –ve voltage (reducing V P ). For V DS >V D(SAT), I D becomes nearly saturated at value as I DS.
Beyond pinch-of, with –ve V GS, I DS is Where R AP (V GS ) is the effective resistance of the conducting n-channel from A to P, which depends on channel thickness and hence V GS. When V GS = -V P = -5V with V DS = 0, the two depletion layers touch over the entire channel length and the whole channel is closed. The channel said to be off.
There is a convenient relationship between I DS and V GS. Beyond pinch-off Where I DSS is drain current when V GS = 0 and V GS(off) is defined as –V P, that is gate-source voltage that just pinches off the channel. The pinch off voltage V P here is a +ve quantity because it was introduced through V DS(sat). V GS(off) however is negative, -V P.
The transconductance curve The process for plotting transconductance curve for a given JFET: Plot a point that corresponds to value of V GS(off). Plot that corresponds to value of I DSS. Select 3 or more values of V GS between 0 V and V GS(off). For value of V GS, determine the corresponding value of I D from Plot the point from (3) and connect all the plotted point with a smooth curve.
MOSFETs and Their Characteristics The metal-oxide semiconductor field effect transistor has a gate, source, and drain just like the JFET. The drain current in a MOSFET is controlled by the gate- source voltage V GS. There are two basic types of MOSFETS: the enhancement-type and the depletion-type. The enhancement-type MOSFET is usually referred to as an E-MOSFET, and the depletion-type, a D-MOSFET. The MOSFET is also referred to as an IGFET because the gate is insulated from the channel.
Fig (a) shows the construction of an n-channel, enhancement-type MOSFET. The p-type substrate makes contact with the SiO2 insulator. Because of this, there is no channel for conduction between the drain and source terminals.
Unijunction Transistor (UJT) Simple two layer transistor Operates using the principle of avalanche breakdown producing a saw tooth output Used to trigger an SCR or TRIAC Also used within pulse circuitry Output from photocells, thermistors, and other transducers can be used to trigger
SCR - Continued Three terminals anode - P-layer cathode - N-layer (opposite end) gate - P-layer near the cathode Three junctions - four layers Connect power such that the anode is positive with respect to the cathode - no current will flow NOTE: Blocked by the reverse bias of junction 2
SCR - Continued Positive potential applied to the gate Current will flow - TURNED-ON Once turned on, gate potential can be removed and the SCR still conducts CALLED LATCHING Holding current maintains latch