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Modeling Sequential Logic Ando KI June 2009
Copyright © 2009 by Ando KiModule overview ( 2 ) Typical Sequential Components D Flip-Flop Counter Shift Register
Copyright © 2009 by Ando KiModule overview ( 3 ) D Flip-Flop Description The D flip-flop is an edge-triggered memory device (cell primitive) that transfers a signals value on its D input, to its Q output, when an active edge transition occurs on its clock input. The output value is held until the next active clock edge. DCKQQ X0Q_ X1 D CK Q Truth tableCircuit symbol Q
Copyright © 2009 by Ando KiModule overview ( 4 ) D Flip-Flop module dff ( CK, D, Q ); inputCK; inputD; outputQ; regQ; CK) Q <= D; endmodule Verilog coding Modeling a D Flip-Flop
Copyright © 2009 by Ando KiModule overview ( 5 ) D Flip-Flop Simulation Go to../project_sequential/dff Run RunMe.bat Note that MODEL_TECH environment variable should be defined, which reflects where ModelSim is installed. SET MODEL_TECH=C:\Modeltech_xe_starter SET MODEL_TECH=C:\Modeltech_se
Copyright © 2009 by Ando KiModule overview ( 6 ) D Flip-Flop Waveform
Copyright © 2009 by Ando KiModule overview ( 7 ) Counter Description A register that goes through a predetermined sequence of binary values, upon the application of input pulses on one ore more inputs, is called a counter. Counters count the number of occurrences of an event.
Copyright © 2009 by Ando KiModule overview ( 8 ) Counter module counter ( clk, reset, count, enable ); input clk; input reset; input enable; output [7:0] count; reg [7:0] count; clk or posedge reset) begin if (reset) count <= 0; else if (enable) count <= count + 1; end endmodule Verilog coding Modeling a 8bit counter
Copyright © 2009 by Ando KiModule overview ( 9 ) Counter Simulation Go to../project_sequential/counter Run RunMe.bat
Copyright © 2009 by Ando KiModule overview ( 10 ) Counter Waveform
Copyright © 2009 by Ando KiModule overview ( 11 ) Shift Register Description Shift register is a group of flip flops set up in a linear fashion which have their inputs and outputs connected together in such a way that the data are shifted down the line when the circuit is activated. Shift register
Copyright © 2009 by Ando KiModule overview ( 12 ) Shift Register module shift_register (clk, shift, sr_in, sr_out); input clk, shift; input sr_in; output sr_out; reg [7:0] sr; clk) begin if (shift == 1'b1) begin sr[7:1] <= sr[6:0]; sr <= sr_in; end assign sr_out = sr; endmodule Verilog coding Modeling an 8-bit shift-left register with a positive-edge clock, serial in, and serial out
Copyright © 2009 by Ando KiModule overview ( 13 ) Shift Register Simulation Go to../project_sequential/shift_register Run RunMe.bat
Copyright © 2009 by Ando KiModule overview ( 14 ) Shift Register Waveform
Modeling Combinational Logic Ando KI June 2009. Copyright © 2009 by Ando KiModule overview ( 2 ) Typical Combinational Components Multiplexer Encoder.
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Verilog RTL Coding Guideline Ando KI June 2009. Copyright © 2007-2009 by Ando KiLecture overview ( 2 ) Contents Purposes of coding guidelines Principles.
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