Modeling Combinational Logic Ando KI June 2009. Copyright © 2009 by Ando KiModule overview ( 2 ) Typical Combinational Components Multiplexer Encoder. - презентация

1 Modeling Combinational Logic Ando KI June 2009

2 Copyright © 2009 by Ando KiModule overview ( 2 ) Typical Combinational Components Multiplexer Encoder Decoder Comparator ALU

3 Copyright © 2009 by Ando KiModule overview ( 3 ) Multiplexer Description A multiplexer (or mux) selectively passes the value of one, of two or more input signals, to the output. One or more control signals which input signals value is passed to the output. SABY 00X0 01X1 1X00 1X11 A B Y S Truth tableCircuit symbol

4 Copyright © 2009 by Ando KiModule overview ( 4 ) Multiplexer module mux2x1 ( A, B, S, Y ); inputA; inputB; inputS; outputY; wireY; assign Y = S ? A : B; endmodule Verilog coding Different ways of modeling a 2-1 multiplexer module mux2x1 ( A, B, S, Y ); inputA; inputB; inputS; outputY; regY; (S or A or B) if (S) Y = A; else Y = B; endmodule module mux2x1 ( A, B, S, Y ); inputA; inputB; inputS; outputY; regY; (S or A or B) case(S) 1b1: Y = A; 1b0: Y = B; endcase endmodule

5 Copyright © 2009 by Ando KiModule overview ( 5 ) Multiplexer Simulation Go to../project_combinational/multiplexer Run RunMe.bat Note that MODEL_TECH environment variable should be defined, which reflects where ModelSim is installed. SET MODEL_TECH=C:\Modeltech_xe_starter SET MODEL_TECH=C:\Modeltech_se

6 Copyright © 2009 by Ando KiModule overview ( 6 ) Multiplexer Waveform

7 Copyright © 2009 by Ando KiModule overview ( 7 ) Encoder Description Encoders are used to encode discrete data into a coded form. Truth table INPUTS OUTPUTS A7A6A5A4A3A2A1A0Y2 Y

8 Copyright © 2009 by Ando KiModule overview ( 8 ) Encoder module encoder_8to3 ( A, Y ); input[7:0]A; output[2:0]Y; reg[2:0]Y; ( A ) if ( A == 8'b ) Y = 0; else if( A == 8'b ) Y = 1; else if( A == 8'b ) Y = 2; else if( A == 8'b ) Y = 3; else if( A == 8'b ) Y = 4; else if( A == 8'b ) Y = 5; else if( A == 8'b ) Y = 6; else if( A == 8'b ) Y = 7; else Y = 3'bx; endmodule Verilog coding Different ways of modeling a 8 to 3 encoder module encoder_8to3 ( A, Y ); input[7:0]A; output[2:0]Y; reg[2:0]Y; ( A ) casex ( A ) 8'b : Y = 0; 8'b : Y = 1; 8'b : Y = 2; 8'b : Y = 3; 8'b : Y = 4; 8'b : Y = 5; 8'b : Y = 6; 8'b : Y = 7; default: Y = 3'bx; endcase endmodule

9 Copyright © 2009 by Ando KiModule overview ( 9 ) Encoder Simulation Go to../project_combinational/encoder Run RunMe.bat

10 Copyright © 2009 by Ando KiModule overview ( 10 ) Encoder Waveform

11 Copyright © 2009 by Ando KiModule overview ( 11 ) Decoder Description Decoders are used to decode data that has been previously encoded using a binary, or possibly other, type of coded format. Truth table INPUTSOUTPUTS A2A1A0Y7Y6Y5Y4Y3Y2Y1Y

12 Copyright © 2009 by Ando KiModule overview ( 12 ) Decoder module decoder_3to8 ( A, Y ); input[2:0]A; output[7:0]Y; reg[7:0]Y; ( A ) casex ( A ) 0: Y = 8'b ; 1: Y = 8'b ; 2: Y = 8'b ; 3: Y = 8'b ; 4: Y = 8'b ; 5: Y = 8'b ; 6: Y = 8'b ; 7: Y = 8'b ; default: Y = 8'bx; endcase endmodule Verilog coding Different ways of modeling a 3 to 8 decoder module decoder_3to8 ( A, Y ); input[2:0]A; output[7:0]Y; reg[7:0]Y; ( A ) if ( A == 0 ) Y = 8'b ; else if( A == 1 ) Y = 8'b ; else if( A == 2 ) Y = 8'b ; else if( A == 3 ) Y = 8'b ; else if( A == 4 ) Y = 8'b ; else if( A == 5 ) Y = 8'b ; else if( A == 6 ) Y = 8'b ; else if( A == 7 ) Y = 8'b ; else Y = 8'bx; endmodule

13 Copyright © 2009 by Ando KiModule overview ( 13 ) Decoder Simulation Go to../project_combinational/decoder Run RunMe.bat

14 Copyright © 2009 by Ando KiModule overview ( 14 ) Decoder Waveform

15 Copyright © 2009 by Ando KiModule overview ( 15 ) Comparator Description A comparator compares two or more inputs using one, or a number of different comparisons. Operators VHDLVerilog Equality=== Relational!= << <= >> =>

16 Copyright © 2009 by Ando KiModule overview ( 16 ) Comparator module comparator ( A, B, Less, Equal, Greater ); input[1:0]A; input[1:0]B; outputLess; outputEqual; outputGreater; regLess; regEqual; regGreater; ( A, B ) if ( A < B ) begin Less <= 1'b1; Equal <= 1'b0; Greater <= 1'b0; end Verilog coding else if ( A == B ) begin Less <= 1'b0; Equal <= 1'b1; Greater <= 1'b0; end else begin Less <= 1'b0; Equal <= 1'b0; Greater <= 1'b1; end endmodule

17 Copyright © 2009 by Ando KiModule overview ( 17 ) Comparator Simulation Go to../project_combinational/comparator Run RunMe.bat

18 Copyright © 2009 by Ando KiModule overview ( 18 ) Comparator Waveform

19 Copyright © 2009 by Ando KiModule overview ( 19 ) ALU Description An arithmetic logic unit (ALU) is the center core of a central processing unit (CPU). It performs a set of arithmetic and logic operations on two input busses. Simple example ALU function table SELOPERATINOS 00Y = A + B 01Y = A and B 10Y = A or B 11Y = shl A (shift left A)

20 Copyright © 2009 by Ando KiModule overview ( 20 ) ALU module alu ( A, B, Sel, Y ); input[1:0]A; input[1:0]B; input[1:0]Sel; output[1:0]Y; reg[1:0]Y; ( A, B, Sel ) case (Sel) 2'b00: Y = A + B; 2'b01: Y = A & B; 2'b10: Y = A | B; 2'b11: Y = A << 1; default: Y = 2'bx; endcase endmodule Verilog coding

21 Copyright © 2009 by Ando KiModule overview ( 21 ) ALU Simulation Go to../project_combinational/alu Run RunMe.bat

22 Copyright © 2009 by Ando KiModule overview ( 22 ) ALU Waveform