® SRAM Overview

® Slide 2 Objectives n What is SRAM? l Memory vs. Storage l Terminology l Static vs. Dynamic l Random vs. Sequential Address 0 Address n n SRAM Features l Asynchronous vs. Synchronous l Pipelined vs. Flow-Through l Burst Mode l Zero Bus Turnaround (ZBT)

® Slide 3 Memory vs. Storage n Memory l Volatile l Fast Access n Storage l Non-volatile l Large Capacity l Slower Access

® Slide 4 Terminology n Bits n Bytes n Density n Width n Depth n Speed Address n. Address 0 Address 1..

® Slide 5 Memory Read & Write READWRITE

® Slide 6 Access Time Time Request Read / Write Data Read / Written Access Time (Speed)

® Slide 7 Static vs. Dynamic Refresh

® Slide 8 n Random Access Memory n Sequentia l Access Memory Random vs. Sequential DATA Control DATA ADDRESS Control

® Slide 9 Static Random Access Memory SRAM 4 M 512K X 8 ADDRESS DATA Control

® Slide 10 Asynchronous vs. Synchronous Addr /Cntrl Data Clock CPUSRAM n Asynchronous SRAM l CPU controls all memory timing n Synchronous SRAM l Clock controls memory timing l CPU enables Addr /Cntrl Data Clock CPUSRAM

® Slide 11 Pipelined vs. Flow-Through n Flow-Through n Pipelined Memory Cells Data Out Memory Cells Data Out Register Data

® Slide 12 Burst Mode n Non-Burst Mode n Burst Mode Address aData (a) SRAM Non-Burst Mode Address a SRAM Burst Mode Data (a) Data (b) Data (c) Data (d)

® Slide 13 Zero Bus Turnaround (ZBT) SRAM Data Bus WriteIdle ReadIdle Bus Turnaround from Write to Read ZBT SRAM Data Bus WriteReadWriteReadWrite No idle time between Reads and Writes

® Slide 14 Summary n Terminology n Data storage types n SRAM features SRAM 4 M 512K X 8 ADDRESS DATA Control