Lecture # 54 1. Computer Architecture Computer Architecture = ISA + MO ISA stands for instruction set architecture is a logical view of computer system. - презентация

1 Lecture # 54 1

2 Computer Architecture Computer Architecture = ISA + MO ISA stands for instruction set architecture is a logical view of computer system. It is related with instruction set design. A computer should have set of instructions so that the user can construct machine language programs to evaluate any function. Categories of instructions Arithmetic logic and shift instructions Transfer / move instructions Program control instructions Input / output instructions 2

3 Machine organization MO stands for machine organization Is a physical view of computer system Includes design of cpu, memory system, I/O system. Input/ output Organization input output organization provides a method for transferring between internal storage and external I/O devices. Peripherals connected to a computer need special communication links for interfacing them with the central processing unit. 3

4 I/O bus connection to I/O devices 4

5 Interface Special hardware components between the CPU and peripherals Supervise and Synchronize all input and output transfers I/O Bus and Interface Modules 1. I/O Bus Data lines Address lines Control lines 2. I/O command : Control Command Status Command Input Command Output Command 5

6 Control command: it is issued to activate the peripheral and to inform it what to do. For example. To rewind the tape or to start the tape moving in forward direction. Status command : used to test various status conditions in the interface and the peripheral. For example, a computer may wish to check the status of peripheral before a transfer is initiated. Output data command: causes the interface to respond by transferring data from the bus into one of its registers. For example processor issues a data output command, the interface responds to address and command and transfers the information from the data lines to its buffer register 6

7 Data input command : opposite of data output command. In this case the interface receives an item of data from the peripheral and places it in its buffer register. The processor checks if the data are available by means of a status command and then issues a data input command, the interface places a data on the data lines, where they are accepted by the processor. 7

8 Memory Hierarchy Main Memory Auxiliary Memory Associative Memory Cache Memory Virtual Memory Memory Management Hardware MEMORY ORGANIZATION 8

9 MEMORY HIERARCHY Magnetic tapes Magnetic disks I/O processor CPU Main memory Cache memory Auxiliary memory Register Cache Main Memory Magnetic Disk Magnetic Tape Memory Hierarchy is to obtain the highest possible access speed while minimizing the total cost of the memory system Memory Hierarchy 9

10 MAIN MEMORY RAM and ROM Chips Typical RAM chip Typical ROM chip Chip select 1 Chip select 2 Read Write 7-bit address CS1 CS2 RD WR AD x 8 RAM 8-bit data bus CS1 CS2 RD WR 0 0 x x 0 1 x x x 1 1 x x Memory function Inhibit Write Read Inhibit State of data bus High-impedence Input data to RAM Output data from RAM High-impedence Chip select 1 Chip select 2 9-bit address CS1 CS2 AD x 8 ROM 8-bit data bus Main Memory 10

11 MEMORY ADDRESS MAP RAM 1 RAM 2 RAM 3 RAM 4 ROM F FF F FF FF Component Hexa address x x x x x x x x x x x x x x x x x x x x x x x x x x x x 1 x x x x x x x x x Address bus Memory Connection to CPU - RAM and ROM chips are connected to a CPU through the data and address buses - The low-order lines in the address bus select the byte within the chips and other lines in the address bus select a particular chip through its chip select inputs Address space assignment to each memory chip Example: 512 bytes RAM and 512 bytes ROM Main Memory 11

12 CONNECTION OF MEMORY TO CPU Main Memory CS1 CS2 RD WR AD7 128 x 8 RAM 1 CS1 CS2 RD WR AD7 128 x 8 RAM 2 CS1 CS2 RD WR AD7 128 x 8 RAM 3 CS1 CS2 RD WR AD7 128 x 8 RAM 4 Decoder 3210 WRRD Address bus Data bus CPU CS1 CS2 512 x 8 ROM AD Data 12