Multi-Port Memory Products Product Line Update

Presentation Outline Why IDT for Multi-Ports? 2.5V Dual-Ports IDTs x36 Multi-Port Family Bank-Switchable Dual-Port Family IDTs Synchronous FourPort Roadmaps for Multi-Ports NE W Update s

Why Look to IDT for Multi-Port Memory Solutions? Superior Track Record on Multi-Ports –IDT is the Industry Leader in Multi-Ports…for +15 Years –Set nearly all Performance/Feature Standards for Industry –Breadth of Portfolio…Over 150 Multi-Port Products Unmatched Performance and Range of Solutions –Width: x8, x9, x16, x18, x36 –Speed: up to 200 MHz sync, 10 ns async 2ports x 36 bits x 200 MHz = 14 Gb/sec –Density: 8 Kb up to 9 Mb –Upgrade Path: x36 Family supports 0.5 Mb to 9 Mb+ –Voltage: 5V, 3.3V, 2.5V, 3.3V with selectable 3.3V/2.5V I/Os –Functionality: Bank-Switchables, FourPorts, SARAMs… = Best in Industry

Multi-Ports: Markets Served 18% 8% 7% 24% 27% 16% Mobile/Wireless Core/Metro Storage Area Networks Enterprise Broadband Miscellaneous BTS, BTS-C, RNC, MSC, Terminals Graphics, Military, Medical, etc. Storage (RAID), Directors/Switches Switches, Routers (ATM, FR, TDM) VPN, VoPN, 100 Mbps ES DSLAM Segment Sample Application

FourPort Dual-Ports Multi-Port Products Bank-Switchable Dual-Ports Async Sync Async Sync Async Sync SARAM

Special Functions AsynchronousAsynchronousFourPort SARAM Multi-Port Portfolio Bank Switchable 5V x8:8Kb to 1Mb x9:18Kb to 1Mb x16:32Kb to 1Mb x18:72Kb to 1Mb 5V x8:8Kb to 1Mb x9:18Kb to 1Mb x16:32Kb to 1Mb x18:72Kb to 1Mb 3.3V x8:8Kb to 1Mb x16:32Kb to 1Mb x18:72Kb to 1Mb 3.3V x8:8Kb to 1Mb x16:32Kb to 1Mb x18:72Kb to 1Mb 3.3V/2.5V* x18:1Mb to 9Mb x36:1Mb to 9Mb 3.3V/2.5V* x18:1Mb to 9Mb x36:1Mb to 9Mb SynchronousSynchronous 5V x8:256Kb to 1Mb x9:36Kb to 1Mb x16:256Kb to 1Mb x18:576Kb to 1Mb 5V x8:256Kb to 1Mb x9:36Kb to 1Mb x16:256Kb to 1Mb x18:576Kb to 1Mb 3.3V x8:8Kb to 1Mb x9:36Kb to 1Mb x16:32Kb to 1Mb x18:72Kb to 1Mb 3.3V x8:8Kb to 1Mb x9:36Kb to 1Mb x16:32Kb to 1Mb x18:72Kb to 1Mb 3.3V/2.5V* x18:576Kb to 9Mb x36:576Kb to 9Mb 3.3V/2.5V* x18:576Kb to 9Mb x36:576Kb to 9Mb * - Core is 2.5V or 3.3V, I/Os are selectable 3.3V/2.5V Future Directions Sync 2.5V/1.8V x36 at 9 Mb, 18 MbSync 2.5V/1.8V x36 at 9 Mb, 18 Mb Tailored functions for target marketsTailored functions for target markets Specialized configurations for specific applicationsSpecialized configurations for specific applications 2.5V x8:64Kb to 128Kb x9:72Kb to 144Kb x16:64Kb to 128Kb x18:72Kb to 144Kb 2.5V x8:64Kb to 128Kb x9:72Kb to 144Kb x16:64Kb to 128Kb x18:72Kb to 144Kb 2.5V x9:72Kb to 144Kb x18:72Kb to 144Kb 2.5V x9:72Kb to 144Kb x18:72Kb to 144Kb New

True Dual-Port Architectures Advanced Functions High Performance Function-compatible with 5V and 3.3V offerings Excellent mix of cost and function True Dual-Port Architectures Advanced Functions High Performance Function-compatible with 5V and 3.3V offerings Excellent mix of cost and function

New 2.5V Dual-Ports 2.5V power supply for both core and I/Os Fully pin and function-compatible with corresponding 5V and 3.3V devices in TQFP packages Also available in 10mm x 10mm fpBGA to minimize boardspace requirements

New 2.5V Dual-Ports 8 asynchronous configurations... as fast as 20 ns 70T058Kx8 70T0616Kx8 70T158Kx9 70T1616Kx9 70T244Kx16 70T258Kx16 70T344Kx18 70T358Kx18 4 synchronous configurations... as fast as 83 MHz 70T91598Kx9 70T916916Kx9 70T93494Kx18 70T93598Kx18

True Dual-Port and Bank- Switchable Architectures Advanced Functions High Performance Dense Storage Capacity Excellent Upgrade Path True Dual-Port and Bank- Switchable Architectures Advanced Functions High Performance Dense Storage Capacity Excellent Upgrade Path

x36 Multi-Port SolutionsAsyncSync Sync Bank- Switchable x18x36x18x36x18X36 0.5M 70V337970V3569 1M 70V63870V65770V338970V3579 2M 70V63970V65870V339970V358970V739970V7589 4M 70V63170V65970V331970V359970V731970V7599 9M 70T63370T65170T333970T351970V733970V7519 = Future product V = 3.3V core with selectable 3.3V/2.5V I/O T = 2.5V core with selectable 3.3V/2.5V I/O Common Packages/Footprints for Powers, Grounds, I/Os, and Controls = New Release

A True Family of Dual-Ports Fastest Speeds –Sync at 200 MHz –Async at 10 ns tAA Multiple Depth/Width Combinations –Density from 0.5Mb up to 9Mb –X36, x18, x9 configurations Common package for x36, x18 in BGA JTAG Selectable 3.3V / 2.5V I/Os

Roadmap to Higher Density* = 0.5 Mb = 1 Mb = 2 Mb = 4 Mb All other pins are common footprint (sync, async, x36, x18) for I/Os, Controls, and Power/Ground All other pins are common footprint (sync, async, x36, x18) for I/Os, Controls, and Power/Ground *BF208 shown… DR208, BC256, DD144, and PK128 provide similar upgrade capabilities = 9 Mb 15 mm

1.0 mm pitch BGA 1.4 mm thick 256-ball (16 x 16) Additional NCs for future upgrades = V DD or V SS Signal Pins grouped to outer three rows to facilitate board routing, improve thermal performance 17 mm

x36 Multi-Port Solutions

JTAG Support Defined by IEEE pins - TDI, TDO, TMS, TCK, TRST# Our x36 Family devices support: –BYPASS, IDCODE, EXTEST, HIGHZ, and SAMPLE/PRELOAD –Internally biased to turn JTAG off if pins are left floating (or can tie/hold TRST# low) compliantcompatibleWe are JTAG compliant, not just compatible

New 9 Mb Async True Dual-Ports x36 and x18 configurations, 9 Mb and 4 Mb 2.5V core, selectable 2.5V/3.3V I/Os 10 ns Access Traditional Advanced Functions –Busy(Master and Slave modes) –Interrupts –Semaphores New Function –Sleep Mode

Asynchronous Sleep Mode Sleep Mode... –Offset higher current draw associated with higher chip densities –Increased compatibility with advanced memory controllers How does the Sleep Mode work? –Asynchronous Input Signal which deselects RAM –Inputs can toggle without affecting Sleep current (I ZZ ) –All Outputs in High-Z state –Timing Parameters tZZS (Sleep Mode Set Time) = tAA (Min.) (i.e., 10 ns on fastest device) tZZR (Sleep Mode Recovery Time) = tAA (Min.)

New 9 Mb Sync True Dual-Ports x36 and x18 configurations, 9 Mb and 4 Mb 2.5V core, selectable 2.5V/3.3V I/Os 200 MHz operations New Functions –Sync Interrupts (Mailbox function) –Collision Detection –Sleep Mode

Synchronous Mailbox Interrupt New Interrupt function... –Facilitate port-to-port coordination (hand-shaking) –Has been implemented without degradation of performance –Improves compatibility with async multi-port offerings How does the Interrupt work? –Similar function to our existing Asynchronous parts EXCEPT Output Flag is Synchronous Address Location 3FFFE Mailbox Interrupt for Left port (INT L ) Address Location 3FFFF Mailbox Interrupt for Right port (INT R ) –Timing Parameters (For 200 MHz) t INS (Interrupt Flag Set Time) = 6 ns t INR (Interrupt Flag Reset Time) = 6 ns

Synchronous Collision Detection Collision Detection... –Developed in response to customer requests –Has been implemented with no degradation of performance –Very useful for customers doing burst accesses What is it? –Synchronous Output Flag which notifies the user that a simultaneous access has occurred at one of the preceding address locations Both Ports Reading NO FLAG ON EITHER PORT 1 Port Reading & 2nd port Writing FLAG ON READING PORT Both ports Writing FLAG ON BOTH PORTS –Flag is pipelined and will be output two cycles later –Timing Parameters (For 200 MHz) t COLS (Collision Flag Set Time) = 3.4 ns, Same as t CD2 t COLR (Collision Flag Reset Time) = 3.4 ns, Same as t CD2

Port A MEMORYARRAY Port B Read Read Read / Write Write Traditional Sync Functionality

Port A MEMORYARRAY Port B Read Read Write Read Flag Write Read Write Write Collision Detection

Synchronous Sleep Mode Sleep Mode... –Offset higher current draw associated with higher chip densities –Increased compatibility with advanced memory controllers How does the Sleep Mode work? –Asynchronous Input Signal (does not have to align on clock edge) which deselects RAM –Clocks can continue running without affecting Sleep current (I ZZ ) –All Outputs in High-Z state –All Inputs allowed to Toggle –Timing Parameters tZZSC (Sleep Mode Set Cycles) = 2 cycles (Min.) tZZRC (Sleep Mode Recovery Cycles) = 3 Cycles (Min.)

Innovative Architecture More Aggressive Cost-per-Bit Higher Performance Denser Storage Capacity Excellent Upgrade Path Innovative Architecture More Aggressive Cost-per-Bit Higher Performance Denser Storage Capacity Excellent Upgrade Path

Definition What is a Bank-Switchable Dual-Ported SRAM? True SRAM core, surrounded by multiplex circuits Memory internally partitioned into banks Simultaneous access to separate banks only Intermediate step between muxed SRAM and full Dual- Port - Densest and Lowest cost-per-bit Dual-Port x36 offerings pin-compatible with full Dual-Ports

COMPARISON: BSDP and Standard Dual-Port Standard Dual-Port Two ports access one common RAM array Simultaneous Access from both ports to the same cell Memory arbitration at the cell level >2x the bandwidth of SRAM Memory Array LEFT PORT CONTROLS RIGHT PORT CONTROLS Left Port Access Right Port Access Bank-Switchable DP SRAM Two ports access Banks of common RAM array Simultaneous Access from both ports to separate banks Memory arbitration at the Bank level >2x the bandwidth of SRAM Highest Density and Lowest Price Dual-Port solution in the industry! Memory Array LEFT PORT CONTROLS RIGHT PORT CONTROLS Bank 0 Bank 1 Bank 2 Bank n Left Port Access Right Port Access

Synchronous BSDP BA 0L - BA 5L A 0L - A 11L BA 0R - BA 5R A 0R - A 11R 64 Banks MUX = Cannot Match during Access = Dont Care Upgrade to BSDP functionality: –Mux is now steered by bank address pins, not by external bank select pins –Increased number of banks (now 64 banks, regardless of density) Like earlier generation, sync BSDP relies on external arbitration –Each internal bank is true SRAM –Simultaneous access to same bank blocks both ports

True FourPort Architecture Advanced Functions High Performance Dense Storage Capacity Increased Port Count True FourPort Architecture Advanced Functions High Performance Dense Storage Capacity Increased Port Count

Synchronous FourPort Port Functions (each port): –Dual chip enables –Independent clock input –Full boundary counter –Maskable counter register –Address readback function –Counter-based interrupt –Mailbox interrupt –x9 byte controls Device Functions: –JTAG –Memory Built-in Self-Test (MBIST) –Master Reset Two Package Options –BC-256 (1.00 mm pitch) –BG-272 (1.27mm pitch) 64Kx18 3.3V 200 MHz Controls Inputs/Outputs Controls Inputs/Outputs Controls Inputs/Outputs Controls Inputs/Outputs IDT70V5388IDT70V5388

Synchronous FourPort - IDT70V V MHz -- 64Kx18 Pin and function-compatible with QuadPort in 272-pin BGA –Independent clock domains –Advanced counter functions (masks, counter readback) –Interrupts –MBIST and JTAG Significant performance enhancements –Full support of advanced counter functions at 0.5Mb and 1Mb (QP supports 1Mb only) –MBIST at 200 MHz in 14.8M cycles (QP at 50 MHz in 31.2M cycles) –Operating current at 133 MHz: IDT: 300 mA typical, 460 mA maxQP: 350 mA typical, 700 mA max Power reduction of 15% to 30% in like operating conditions –200 MHz operations per port, compared to QP max of 133 MHz 40% higher bandwidth 40% higher bandwidth (14 Gbps vs. 9.6 Gbps) –Smaller package option in the 256-pin BGA BG-272 (IDT, QP)BC-256 (IDT) 27mm x 27mm, 1.27mm pitch17mm x 17mm, 1.00mm pitch 729mm 2 289mm 2 Boardspace savings of nearly 60%

FourPort Applications Switching –Write any port, read from any other port –Separate, independent clock domains and frequencies –Mailbox and specialized counter controls –Ability to combine ports (e.g., one x36 port to two x18 ports) Data muxing and demuxing –One port write, many read and/or many write, one read –Maskable counters Multi-component shared memory storage to support CPUs, DSPs, NPUs, FPGAs, ASICs... –Independent, simultaneous, random access from all ports at frequencies up to 200 MHz –Byte controls to facilitate bus matching –Mailbox functions BG-272 BC-256

IDT - the Proven Leader The undisputed leader in market share The technology leader with the worlds highest performance multi-ports We continue to set the standards Density Performance Features Powering Whats Next IDT is committed to Powering Whats Next