Chapter 6 Digital Arithmetic: Operations and Circuits ECE 221 Intro. Digital Systems Fall Semester 2002 ECE Department, UMASS-Amherst Prof. Hill Prof. - презентация

1 Chapter 6 Digital Arithmetic: Operations and Circuits ECE 221 Intro. Digital Systems Fall Semester 2002 ECE Department, UMASS-Amherst Prof. Hill Prof. Gong

2 Objectives Addition, subtraction, multiplication, and division of two binary numbers. Addition and subtraction of hexadecimal numbers Difference between binary addition and OR addition. Comparison among three different systems for representing signed numbers. Manipulate signed binary numbers using the 2s – complement system. BCD adder circuit and addition process. Basic operation of an arithmetic/logic unit

3 6-1 Binary Addition The addition of two binary numbers is performed in exactly the same manner as the addition of decimal numbers. Least-significant-digit first. Carry of 1 into the next position may be needed. 4 different cases for binary addition The operations of subtraction, multiplication, and division actually use only addition as their basic operation

4 Example

5 Review Question Add the following pairs of binary numbers. – – –

6 Representing signed numbers (6.2) C onsiderations: representing both positive and negative numbers; efficient computation. Sign-magnitude system

7 Sign-magnitude system: represents + and – numbers, but we need to design special circuits to add positive and negative numbers. ex: 5 + (-5) = 0 use 8 bit signed-binary numbers and add using full-adder circuits : ( 5) (-5) _____________________ (-10)

8 1s complement system –Change each 0 to 1, and each 1 to 0. –Example (45) original binary number (-45) complement each bit (45) (-45) ____________________ Add one to this result, get zero.

9 2s complement of a binary number: –Take the 1s complement of the number –Add 1 to the least-significant-bit position

10 Representing signed numbers using 2s complement form If the number is positive, the magnitude is represented in its positional-weighted binary form, and a sign bit of 0 is placed in front of the MSB. If the number is negative, the magnitude is represented in its 2s complement form, and a sign bit of 1 is placed in front of the MSB.

11 example

12 Example Represent each of the following signed decimal numbers as a signed binary number in the 2s- complement system. Use a total of five bits including the sign bit. (a) +13 (b) –9 (c) +3 (d) –2 (e) -8

13 Negation Negation is the operation of converting a postive number to its negative equivalent or a negative number to its positive equivalent. We negate a signed binary number by 2s-complementing it. Example –Each of the following numbers is a signed binary number in the 2s-complement system. Determine the decimal value in each case: (a)01100 (b) (c)10001

14 Special case in 2s-complement representation Whenever a signed number has a 1 in the sign bit and all 0s for the magnitude bits, its decimal equivalent is –2 N, where N is the number of bits in the magnitude. The complete range of values that can be represented in the 2s-complement system having N magnitude bits is –2 N to +(2 N - 1). What is the range of unsigned decimal values that can be represented in a byte? What is the range of signed decimal values that can be represented in a byte?

15 Review Questions Represent each of the following values as an eight-bit signed number in the 2s-complement system (a)+13 (b) –7 (c)-128 Each of the following is a signed binary number in the 2s- complement system. Determine the decimal equivalent for each. (a) (b) (c) What range of signed decimal values can be represented in 12 bits(including the sign bit)? How many bits are required to represent decimal values ranging from –50 to +50? What is the largest negative decimal value that can be represented by a two-byte number? Perform the 2s-complement operation on each of the following. (a)10000 (b) ©1000 Define the negation operation

16 6-3 Addition in the 2s- complement system Case I: Two Postive Numbers (augend) (addend) (sum = +13) Sign bits

17 Addition, cont. Case II: Positive Number and Smaller Negative Number (augend) (addend) Sign bits This carry is disregarded; the result is 01001(sum=+5)

18 Addition, cont. Case III: Positive Number and Larger Negative Number (sum = -5) Negative sign bit

19 Addition, cont. Case IV: two negative Numbers Sign bit This carry is disregarded; the result is 10011(sum =-13)

20 Addition, cont. Case V: Equal and Opposite Numbers Disregard; the result is 00000(sum = +0)

21 Review Questions Assume the 2s complement system for both questions –True or False: Whenever the sum of two signed binary numbers has a sign bit of 1, the magnitude of the sum is in 2s complement form. –Add the following pairs of signed numbers. Express the sum as a signed binary number and as a decimal number (a) (b)

22 6-4 Subtraction in the 2s- complement System The procedure for subtracting one binary number(the subtrahend) from another binary number(the minuend) –Negate the subtrahend. This will change the subtrahend to its equivalent value of opposite sign. –Add this to the minuend. The result of this addition will represent the difference between the subtrahend and the minuend.

23 Arithmetic Overflow When two positive or two negative numbers are being added, an overflow could occur if there is a carry happening to the sign-bit position. Overflow can occur when the minuend and subtrahend have different signs.

24 Review Questions Perform the subtraction on the following pairs of signed numbers using the 2s-complement system. Express the results as signed binary numbers and as decimal values. (a) (b) How can arithmetic overflow be detected when signed numbers are being added? Subtracted?

25 6-5 Multiplication of Binary numbers The same manner as the multiplication of decimal numbers multiplicand = multiplier= final product = 99 10

26 Multiplication in the 2s- Complement System If the two numbers to be multiplied are positive, they are already in true binary form and are multiplied as they are. When the two numbers are negative, they will be in 2s-complement form. Each is converted to a positive number, and then the two numbers are multiplied. The product is kept as a positive number and is given a sign bit of 0. When one of the number is positive and the other is negative, the negative number is first converted to a positive magnitude by taking its 2s complement. The product will be in true-magnitude form, should be changed to 2s complement form and given a sign bit of 1.

27 Review Question Multiply the unsigned numbers 0111 and 1110

28 6-6 Binary Division The same as for decimal numbers---long division The division of signed numbers is handled in the same way as multiplication.

29 6-7 BCD ADDITION Sum Equals 9 or Less

30 6-8 Hexadecimal Arithmetic Hex Addition –Add the two hex digits in decimal, mentally inserting the decimal equivalent for those digits larger than 9. –If the sum is 15 or less, it can be directly expressed as a hex digit. –If the sum is greater than or equal to 16, subtract 16 and carry a 1 to the next digit position. Examples –Add the hex numbers 58 and 24 –Add the hex numbers 58 and 4B –Add 3AF and 23C

31 Hex subtraction How to get the 2s-complement of a hex number? Convert to binary, take the 2s complement of the binary equivalent, and then convert back to hex. 73A C6

32 A quicker procedure: subtract each hex digit from F; then add 1. F F F -7-3-A 8 C C6 } Subtract each digit from F Add 1 Hex equivalent of 2s complement

33 Example Subtract 3A5 16 from

34 Review Questions Add 67F+2A4 Subtract 67F-2A4 Which of the following hex numbers represent positive values: 2F, 77EC, C000, 6D, FFFF?

35 6-9 Arithmetic Circuits

36 6-10 Parallel binary adder

37 Parallel adder

38 Review Questions How many inputs does a full adder have? How many outputs? Assume the following input levels in Parallel Adder: –A 4 A 3 A 2 A 1 A 0 =01001; B 4 B 3 B 2 B 1 B 0 =00111; C 0 =0 (a)What are the logic levels at the outputs of FA#2? (b)What is the logic level at the C 5 output?

39 6-11 Design of a Full Adder Truth table for a full-adder circuit

40 K Mappings for the full-adder outputs

41 Complete circuitry for a full adder

42 6-12 Complete parallel adder with registers

43 Sequence of operations [A]=0000 [M]-> [B] [S] * ->[A] [M]->[B] [S]->[A]

44 Review Questions Suppose that four different four-bit numbers are to be taken from memory and added by the circuit in the last figure, how many CLEAR pulses will be needed? How many TRANSFER pulses? How many LOAD pulses? Determine the contents of the A register after the following sequence of operations: – [A]=0000, [0110]->[B], [S]->[A] [1110]->[B], [S]->[A]

45 6-14 Integrated-Circuit Parallel Adder

46 Example Determine the logic levels at the inputs and outputs of the eight-bit adder in Figure 6-10(b) when is added to

47 Review Questions How many 74HC283 chips are needed to add two 20-bit numbers? If a 74HC283 has a maximum propagation delay of 30 ns from C 0 to C 4, what will be the total propagation delay of a 32-bit adder constructed from 74HC283s? What will be the logic level at C 4 in Last Example?

48 6-15 2s Complement system The operations of addition and subtraction of signed numbers can be performed using only the addition operation if we use the 2s complement form to represent negative numbers.

49 Addition

50 Subtraction

51 Combined Addition and Subtraction

52 Review Questions Why does C 0 have to be a 1 in order to use the adder circuit in Figure 6-12 as a subtractor? Assume that [A]=0011 and [B]=0010 in Figure If ADD=1 and SUB=0, determine the logic levels at the OR gate outputs. Repeat question 2 for ADD=0, SUB=1 Ture or False: When the adder/Subtractor circuit is used for subtraction, the 2s complement of the subtrahend appears at the input of the adder.

53 6-16 BCD ADDER Add the BCD code groups for each decimal digit position; use ordinary binary addition. For those positions where the sum is 9 or less, the sum is in proper BCD form and no correction is needed When the sum of two digits is greater than 9, a correction of 0110 should be added to that sum to produce the proper BCD result. This will produce a carry to be added to the next decimal position. –A 3 A 2 A 1 A 0 BCD code group –B 3 B 2 B 1 B 0 BCD code group S 4 S 3 S 2 S 1 S 0 straight binary sum

54 Truth table S4S4 S3S3 S2S2 S1S1 S0S (10) 01011(11) 01100(12) 01101(13) 01110(14) 01111(15) 10000(16) 10001(17) 10010(18) X=S 4 +S 3 (S 2 +S 1 )

55 A BCD adder

56 Example Determine the inputs and outputs when the below circuit is used to add to Assume CARRY IN=0.

57 Review Questions What are the three basic parts of a BCD adder circuit? Describe how the BCD adder circuit detects the need for a correction and executes it.

58 6-17 ALU Integrated Circuits

59 Operations CLEAR ADD SUBTRACT XOR OR AND PRESET

60 Example Determine the 74HC382 outputs for the following inputs: S 2 S 1 S 0 =010, A 3 A 2 A 1 A 0 =0100, B 3 B 2 B 1 B 0 =0001, and C N =1. Change the select code to 011 and repeat.

61 Expanding the ALU

62 Example How would the arrangement in the last figure have to be changed in order to perform the subtraction(B-A)?

63 Review Questions Apply the following inputs to the ALU of Figure 6-16, and determine the outputs: S 2 S 1 S 0 =001, A 3 A 2 A 1 A 0 =1110, B 3 B 2 B 1 B 0 =1001, C N =1. Change the select code to 011 and C N to 0, and repeat question 1. Change the select code to 110 and repeat question 1. Apply the following inputs to the circuit of Figure 6-17, and determine the outputs: B= , A= Change the select code to 111, and repeat question 4. How many 74HC382s are needed to add two 32-bit numbers?