Скачать презентацию

Идет загрузка презентации. Пожалуйста, подождите

Презентация была опубликована год назад пользователемИнна Виноградова

1 Xilinx FPGAs - 1 trend toward higher levels of integration Evolution of Implementation Technologies zDiscrete devices: relays, transistors (1940s-50s) zDiscrete logic gates (1950s-60s) zIntegrated circuits (1960s-70s) ye.g. TTL packages: Data Book for 100s of different parts yMap your circuit to the Data Book parts zGate Arrays (IBM 1970s) yCustom integrated circuit chips yDesign using a library (like TTL) yTransistors are already on the chip yPlace and route software puts the chip together automatically y+ Large circuits on a chip y+ Automatic design tools (no tedious custom layout) y- Only good if you want 1000s of parts

2 Xilinx FPGAs - 2 Gate Array Technology (IBM s) zSimple logic gates yUse transistors to implement combinational and sequential logic zInterconnect yWires to connect inputs and outputs to logic blocks zI/O blocks ySpecial blocks at periphery for external connections zAdd wires to make connections yDone when chip is fabbed xmask-programmable yConstruct any circuit

3 Xilinx FPGAs - 3 Programmable Logic zDisadvantages of the Data Book method yConstrained to parts in the Data Book yParts are necessarily small and standard yNeed to stock many different parts zProgrammable logic yUse a single chip (or a small number of chips) yProgram it for the circuit you want yNo reason for the circuit to be small

4 Xilinx FPGAs - 4 Programmable Logic Technologies zFuse and anti-fuse yFuse makes or breaks link between two wires yTypical connections are ohm yOne-time programmable (testing before programming?) yVery high density zEPROM and EEPROM yHigh power consumption yTypical connections are 2K-4K ohm yFairly high density zRAM-based yMemory bit controls a switch that connects/disconnects two wires yTypical connections are.5K-1K ohm yCan be programmed and re-programmed in the circuit yLow density

5 Xilinx FPGAs - 5 Programmable Logic zProgram a connection yConnect two wires ySet a bit to 0 or 1 zRegular structures for two-level logic (1960s-70s) yAll rely on two-level logic minimization yPROM connections - permanent yEPROM connections - erase with UV light yEEPROM connections - erase electrically yPROMs xProgram connections in the _____________ plane yPLAs xProgram the connections in the ____________ plane yPALs xProgram the connections in the ____________ plane

6 Xilinx FPGAs - 6 Making Large Programmable Logic Circuits zAlternative 1 : CPLD yPut a lot of PLDS on a chip yAdd wires between them whose connections can be programmed yUse fuse/EEPROM technology zAlternative 2: FPGA yEmulate gate array technology yHence Field Programmable Gate Array yYou need: xA way to implement logic gates xA way to connect them together

7 Xilinx FPGAs - 7 Field-Programmable Gate Arrays zPALs, PLAs = Gate Equivalents zField Programmable Gate Arrays = FPGAs yAltera MAX Family yActel Programmable Gate Array yXilinx Logical Cell Array z (s) of Gate Equivalents!

8 Xilinx FPGAs - 8 Field-Programmable Gate Arrays zLogic blocks yTo implement combinational and sequential logic zInterconnect yWires to connect inputs and outputs to logic blocks zI/O blocks ySpecial logic blocks at periphery of device for external connections zKey questions: yHow to make logic blocks programmable? yHow to connect the wires? yAfter the chip has been fabbed

9 Xilinx FPGAs - 9 Tradeoffs in FPGAs zLogic block - how are functions implemented: fixed functions (manipulate inputs) or programmable? ySupport complex functions, need fewer blocks, but they are bigger so less of them on chip ySupport simple functions, need more blocks, but they are smaller so more of them on chip zInterconnect yHow are logic blocks arranged? yHow many wires will be needed between them? yAre wires evenly distributed across chip? yProgrammability slows wires down – are some wires specialized to long distances? yHow many inputs/outputs must be routed to/from each logic block? yWhat utilization are we willing to accept? 50%? 20%? 90%?

10 Xilinx FPGAs Product Term AND-OR Array + Programmable MUX's Programmable polarity I/O Pin Seq. Logic Block Programmable feedback Altera EPLD (Erasable Programmable Logic Devices) zHistorical Perspective yPALs: same technology as programmed once bipolar PROM yEPLDs: CMOS erasable programmable ROM (EPROM) erased by UV light zAltera building block = MACROCELL

11 Xilinx FPGAs - 11 Altera EPLDs contain 8 to 48 independently programmed macrocells Personalized by EPROM bits: Flipflop controlled by global clock signal local signal computes output enable Flipflop controlled by locally generated clock signal + Seq Logic: could be D, T positive or negative edge triggered + product term to implement clear function Altera EPLD

12 Xilinx FPGAs - 12 AND-OR structures are relatively limited Cannot share signals/product terms among macrocells Logic Array Blocks (similar to macrocells) Global Routing: Programmable Interconnect Array 8 Fixed Inputs 52 I/O Pins 8 LABs 16 Macrocells/LAB 32 Expanders/LAB EPM5128: Altera Multiple Array Matrix (MAX)

13 Xilinx FPGAs - 13 LAB Architecture Expander Terms shared among all macrocells within the LAB

14 Xilinx FPGAs - 14 Supports large number of product terms per output Latches and muxes associated with output pins P22V10 PAL

15 Xilinx FPGAs - 15 Rows of programmable logic building blocks + rows of interconnect Anti-fuse Technology: Program Once 8 input, single output combinational logic blocks FFs constructed from discrete cross coupled gates Use Anti-fuses to build up long wiring runs from short segments Actel Programmable Gate Arrays

16 Xilinx FPGAs - 16 Basic Module is a Modified 4:1 Multiplexer Example: Implementation of S-R Latch Actel Logic Module

17 Xilinx FPGAs - 17 Interconnection Fabric Actel Interconnect

18 Xilinx FPGAs - 18 Jogs cross an anti-fuse minimize the # of jobs for speed critical circuits hops for most interconnections Actel Routing Example

19 Xilinx FPGAs - 19 Xilinx Programmable Gate Arrays zCLB - Configurable Logic Block y5-input, 1 output function yor 2 4-input, 1 output functions yoptional register on outputs zBuilt-in fast carry logic zCan be used as memory zThree types of routing ydirect ygeneral-purpose ylong lines of various lengths zRAM-programmable ycan be reconfigured

20 Programmable Interconnect I/O Blocks (IOBs) Configurable Logic Blocks (CLBs)

21 Xilinx FPGAs - 21 The Xilinx 4000 CLB

22 Xilinx FPGAs - 22 Two 4-input functions, registered output

23 Xilinx FPGAs input function, combinational output

24 Xilinx FPGAs - 24 CLB Used as RAM

25 Xilinx FPGAs - 25 Fast Carry Logic

26 Xilinx FPGAs - 26 Xilinx 4000 Interconnect

27 Xilinx FPGAs - 27 Switch Matrix

28 Xilinx FPGAs - 28 Xilinx 4000 Interconnect Details

29 Xilinx FPGAs - 29 Global Signals - Clock, Reset, Control

30 Xilinx FPGAs - 30 Xilinx 4000 IOB

31 Xilinx FPGAs - 31 Xilinx FPGA Combinational Logic Examples zKey: General functions are limited to 5 inputs y(4 even better - 1/2 CLB) yNo limitation on function complexity zExample 2-bit comparator: A B = C D and A B > C D implemented with 1 CLB (GT)F = A C' + A B D' + B C' D' (EQ)G = A'B'C'D'+ A'B C'D + A B'C D'+ A B C D zCan implement some functions of > 5 input

32 Xilinx FPGAs - 32 CLB 5-input Majority Circuit CLB 7-input Majority Circuit Xilinx FPGA Combinational Logic zExamples yN-input majority function: 1 whenever n/2 or more inputs are 1 yN-input parity functions: 5 input/1 CLB; 2 levels yield 25 inputs! CLB 9 Input Parity Logic

33 Xilinx FPGAs - 33 Xilinx FPGA Adder Example zExample y2-bit binary adder - inputs: A1, A0, B1, B0, CIN outputs: S0, S1, Cout Full Adder, 4 CLB delays to final carry out 2 x Two-bit Adders (3 CLBs each) yields 2 CLBs to final carry out

34 Xilinx FPGAs - 34 Computer-Aided Design zCan't design FPGAs by hand yWay too much logic to manage, hard to make changes zHardware description languages ySpecify functionality of logic at a high level zValidation: high-level simulation to catch specification errors yVerify pin-outs and connections to other system components yLow-level to verify mapping and check performance zLogic synthesis yProcess of compiling HDL program into logic gates and flip-flops zTechnology mapping yMap the logic onto elements available in the implementation technology (LUTs for Xilinx FPGAs)

35 Xilinx FPGAs - 35 CAD Tool Path (contd) zPlacement and routing yAssign logic blocks to functions yMake wiring connections zTiming analysis - verify paths yDetermine delays as routed yLook at critical paths and ways to improve zPartitioning and constraining yIf design does not fit or is unroutable as placed split into multiple chips yIf design it too slow prioritize critical paths, fix placement of cells, etc. yFew tools to help with these tasks exist today zGenerate programming files - bits to be loaded into chip for configuration

36 Xilinx FPGAs - 36 Xilinx CAD Tools zVerilog (or VHDL) use to specify logic at a high-level yCombine with schematics, library components zSynopsys yCompiles Verilog to logic yMaps logic to the FPGA cells yOptimizes logic zXilinx APR - automatic place and route (simulated annealing) yProvides controllability through constraints yHandles global signals zXilinx Xdelay - measure delay properties of mapping and aid in iteration zXilinx XACT - design editor to view final mapping results

37 Xilinx FPGAs - 37 Applications of FPGAs zImplementation of random logic yEasier changes at system-level (one device is modified) yCan eliminate need for full-custom chips zPrototyping yEnsemble of gate arrays used to emulate a circuit to be manufactured yGet more/better/faster debugging done than with simulation zReconfigurable hardware yOne hardware block used to implement more than one function yFunctions must be mutually-exclusive in time yCan greatly reduce cost while enhancing flexibility yRAM-based only option zSpecial-purpose computation engines yHardware dedicated to solving one problem (or class of problems) yAccelerators attached to general-purpose computers

Еще похожие презентации в нашем архиве:

Подбираем похожую презентацию...

Готово:

1/27 Chapter 9: Template Functions And Template Classes.

1/27 Chapter 9: Template Functions And Template Classes.

© 2017 MyShared Inc.

All rights reserved.