Parity Generator & Checker Ando KI June 2009

Copyright © 2009 by Ando KiModule overview ( 2 ) Objectives Learn what is parity. Learn how to use Verilog for combinational logic. Learn how to simulate a Verilog design.

Copyright © 2009 by Ando KiModule overview ( 3 ) What is parity? The parity is a redundant information bit associated with a word of N-bit which are transmitted together. The parity bit tells whether Hamming weight (i.e., the number of 1s) in a code- word (i.e, parity+word) is odd or even. Parity generator Parity checker N-bit data word parity Error or not Bit-error can occur.

Copyright © 2009 by Ando KiModule overview ( 4 ) Parity schemes Even-parity scheme makes the number of of 1s to be even including the data and the parity. Parity = 1 if and only if the number of 1 in a word is odd. Odd-parity scheme makes the number of of 1s to be odd including the data and the parity. Parity = 1 if and only if the number of 1 in a word is even. p=W1W2…Wn p=~(W1W2…Wn) error=W1W2…Wnp error=W1W2…Wn)~(p stands for exclusive OR.

Copyright © 2009 by Ando KiModule overview ( 5 ) Parity: specifications Specifications Even/odd selectable Both generator and checker in a single block Input data bit-width: 8-bit (data) Input parity: 1-bit (pin) For generator: 1-bit output (pout) For checker: 1-bit output (error)

Copyright © 2009 by Ando KiModule overview ( 6 ) Parity: pin specifications Pin namewidthIn/outremarks mode1in0 for even, 1 for odd data8inWord to be protected or checked pin1inParity input for parity check pout1outParity output as a result of parity generation error1outParity check result; 1 for error, 0 for OK

Copyright © 2009 by Ando KiModule overview ( 7 ) data pin mode pout error Parity: block and timing diagram parity gen. & checker 8-bit data 1-bit parity-in even/odd 1-bit parity-out 1-bit error data pin mode pout error

Copyright © 2009 by Ando KiModule overview ( 8 ) mode parity error Tester: block and timing diagram tester data mode parity error clk data clk Tester block generates new data at the rising edge of clk. Tester block check data, parity, and error at the falling edge of clk. Then, reports error. Types of error Generator error: check data and parity Checker error: check data, parity, and error. Be sure that the tester block include $stop or $finish in order to stop or terminate the simulation.

Copyright © 2009 by Ando KiModule overview ( 9 ) top Top-level schematic Parity generator and checker data pin mode pout error Parity generator and checker data pin mode pout error tester data mode parity error clock 0 clk Utester UgenUchk

Copyright © 2009 by Ando KiModule overview ( 10 ) Form a team Form a team of three persons (A, B, C). A makes parity.v. B makes tester.v C makes top.v. All together run simulation. data pin mode pout error data pin mode pout error tester data mode parity error clock 0 clk Which one is difficult to build?

Copyright © 2009 by Ando KiModule overview ( 11 ) Requirement Do not use the same algorithm (equation or method) for DUT and test-bench. Use XOR for DUT. Use counting method for test-bench.

Copyright © 2009 by Ando KiModule overview ( 12 ) Tips The system function $random provides a mechanism for generating random numbers. It returns a new 32-bit random number each time it is called. The number is a signed integer, so that it can be positive or negative. Where b is greater than 0, the expression below gives a number in the following range. [(-b+1)-(b-1)]. $random % b; // random number: -59 ~ 59 reg [23:0] var_reg; var_reg = $random % 60; // random number: 00, 01, 10, 11 reg [1:0] var_reg; var_reg = $random & 2h3; // random number of 8-bits. reg [7:0] var_reg; var_reg = $random & 8hFF;

Copyright © 2009 by Ando KiModule overview ( 13 ) Verilog code segments module top; wire mode, parity, error; wire [7:0] data; reg clk; … endmodule module parity ( mode, data, pin, pout, error ); input mode; input [7:0] data; input pin; output pout; output error; … endmodule module tester ( clk, mode, data, parity, error ); input clk; output mode; output [7:0] data; input parity; input error; … endmodule

Copyright © 2009 by Ando KiModule overview ( 14 ) Simulation Simulation using Mentor Graphics ModelSim Simulation steps using ModelSim Simulation with command line mode Simulation through GUI

Copyright © 2009 by Ando KiModule overview ( 15 ) Simulation steps 1. Compile Convert the Verilog source code into an internal format that is ready for ModelSim to simulate. 2. Simulate the internal format by instantiating all the design modules and using a top level stimulus file to drive test signals onto the inputs of your design and inspecting the outputs.

Copyright © 2009 by Ando KiModule overview ( 16 ) ModelSim commands vlib creates a design library. vlog is a Verilog compiler. vsim is a Verilog simulator. vlib vlog [+incdir+ ] [+define+ [= ]] verilog_file_name vsim [-c] [-gui] [-do ] Where –c for command line mode, -gui for GUI mode, and –do instruct the simulator to use command given in the string.

Copyright © 2009 by Ando KiModule overview ( 17 ) Simulation with command-line (1/3) vlib work vlog../design/parity.v vlog../design/tester.v vlog +define+_VCD_../design/top.v vsim -c -do "run -all; finish" work.top Create a design library (directory) with the name of work Compile Verilog design files Run simulator Commands for simulator Design top module Windows batch command file make.bat Commands for simulator

Copyright © 2009 by Ando KiModule overview ( 18 ) Simulation with command-line (2/3) Windows command prompt> make.bat Model Technology ModelSim XE III vlog 6.0a Compiler Nov Compiling module parity Top level modules: parity Model Technology ModelSim XE III vlog 6.0a Compiler Nov Compiling module tester Top level modules: tester Model Technology ModelSim XE III vlog 6.0a Compiler Nov Compiling module top Top level modules: top Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl

Copyright © 2009 by Ando KiModule overview ( 19 ) Simulation with command-line (3/3) # 6.0a # vsim -do {run -all; finish} -c work.top # Loading C:\iTUTOR\eda\modelsim\5.7c\iprvpi.dll # Loading work.top # Loading work.tester # Loading work.parity # run -all; finish # ** Note: Data structure takes bytes of memory # Process time 0.00 seconds # $finish : z:/……/projects/01_project_parity_code/sim/../design/tester.v(39) # Time: 105 ps Iteration: 1 Instance: /top/Utester Windows command prompt> dir make.bat transcript wave.vcd work

Copyright © 2009 by Ando KiModule overview ( 20 ) Invoking GTKwave Invoke GTKWave by clicking wave.vcd twice. Even parity mode

Copyright © 2009 by Ando KiModule overview ( 21 ) Homework Make a realistic environment using channel model that insert noise. Then, let see what happens. data pin mode pout error data pin mode pout error tester data mode parity error clock 0 clk Noise inserter