Verilog Basic Language Constructs - Lexical convention, data types and so on - Ando KI Spring 2009

Copyright © by Ando KiIntroduction to Verilog Basic ( 2 ) Contents BNF Comment Identifier Keyword Operator Number Sting Compiler directives Data types

Copyright © by Ando KiIntroduction to Verilog Basic ( 3 ) BNF: Backus-Naur Form A formal definition for a language syntax is a set of rules for forming valid programs in the language. BNF is the most widely used scheme to define syntax formally. A BNF definition of a language syntax is a set of syntax equations. What is being defined appears on the left, and The definition appears on the right. Alternatives are separated by vertical bars: i.e., a | b stands for a or b. Square brackets indicate optional: [ a ] stands for an optional a. to_be_defined ::= definition_1 | definition_2 [| definition_3] Be defined to be Or, alternatively Optional

Copyright © by Ando KiIntroduction to Verilog Basic ( 4 ) Verilog source text source_text ::= { description } description ::= module_declaration | udp_declaration | config_declaration module_declaration ::= { attribute_instance } module module_identifier [ module_parameter_port_list ] list_of_ports ; { module_item } endmodule module ModG (AA, BB, CC); input AA; inout [7:0] BB; output [7:0] CC; wire a; wire [7:0] b; ModF Umodf (.A(a),.B(b),.C(CC)); endmodule Bold type characters are terminals.

Copyright © by Ando KiIntroduction to Verilog Basic ( 5 ) Verilog lexical tokens Types of lexical tokens White space: spaces, tabs(\t), newlines(\n), and EOF (end of file) Comment Identifier: a unique name (string) given to an object Keyword: predefined non-escaped identifiers that are used to define the language constructs. All keywords are lower-case. Operator Number String: a sequence of characters enclosed by double quotes ( ) and contained on a single line Compiler directives: identifier following the ` character (the ASCII value 0x60, called open quote or accent grave) controls how a compiler should process its input

Copyright © by Ando KiIntroduction to Verilog Basic ( 6 ) Comments A comment is a programming language construct used to embed information in the source code of a computer program and it is ignored by compiler. one-line comment A single line comment begins with // and ends with a newline. block comment A block comment begins with /* and ends with */. // a single comment line // a comment line // another comment line /* a single comment line */ /* a multiple-line comment line 1 line 2 line 3 line 4 */ comment ::= one_line_comment | block_comment one_line_comment ::= // comment_text \n block_comment ::= /* comment_text */ comment_text ::= { Any_ASCII_character }

Copyright © by Ando KiIntroduction to Verilog Basic ( 7 ) Identifier Verilog identifier is a unique name given to an object in a design. Name is case sensitive. Identifier can be simple identifier and escaped identifier. Simple identifier is a sequence of letters (alphabetic characters) and digits (numeric characters) including _ and $. The first character should not be a number or $. Escaped identifier starts with backslash (\) and ends with white space. A means of including any of the printable ASCII characters in an identifier (33 (0x21) ~ 126 (0x7E)). // simple identifier shiftreg_a busa_index Error_confition merger_ab Merger_AB _bus3 N$657 // escaped identifier \busa+index \-clock \**error-condition*** \net1/\net2 \{a,b} \a*(b+c)

Copyright © by Ando KiIntroduction to Verilog Basic ( 8 ) Verilog keywords A keyword is a word or identifier that has a particular meaning to the programming language. Verilog is case-sensitive All Verilog keywords are lower case. However, dont use case sensitive feature since some simulator are case insensitive.

Copyright © by Ando KiIntroduction to Verilog Basic ( 9 ) Verilog-1995 keywords always and assign begin buf bufif0 bufif1 case casex casez cmos deassign default defparam disable edge else end endcase endmodule endfunction endprimitive endspecify endtable endtask event for force forever fork function highz0 highz1 if ifnone initial inout input integer join large macromodule medium module nand negedge nmos nor not notif0 notif1 or output parameter pmos posedge primitive pull0 pull1 pullup pulldown rcmos real realtime reg release repeat rnmos rpmos rtran rtranif0 rtranif1 scalared small specify specparam strong0 strong1 supply0 supply1 table task time tran tranif0 tranif1 tri tri0 tri1 triand trior trireg vectored wait wand weak0 weak1 while wire wor xnor xor

Copyright © by Ando KiIntroduction to Verilog Basic ( 10 ) Verilog-2001/2005 keywords (1/2) always and assign automatic begin buf bufif0 bufif1 case casex casez cell cmos config deassign default defparam design disable edge else end endcase endconfig endfunction endgenerate endmodule endprimitive endspecify endtable endtask event for force forever fork function generate genvar highz0 highz1 if ifnone incdir include initial inout input instance integer join large liblist library localparam macromodule medium module nand negedge nmos nor noshowcancelled not notif0 notif1 or output

Copyright © by Ando KiIntroduction to Verilog Basic ( 11 ) Verilog-2001/2005 keywords (2/2) parameter pmos posedge primitive pull0 pull1 pulldown pullup pulsestyle_onevent pulsestyle_ondetect rcmos real realtime reg release repeat rnmos rpmos rtran rtranif0 rtranif1 scalared showcancelled signed small specify specparam strong0 strong1 supply0 supply1 table task time tran tranif0 tranif1 tri tri0 tri1 triand trior trireg unsigned use vectored wait wand weak0 weak1 while wire wor xnor xor

Copyright © by Ando KiIntroduction to Verilog Basic ( 12 ) Verilog value set ValueMeaning in logic level 0Low logic level or false condition 1High logic level or true condition X, xUnknown logic level Z, zHigh impedance logic level For switch level modeling of MOS devices Driving (signal) strengths Strength1: (for logic 1) supply1, strong1, full1, weak1 Strength0: (for logic 0) supply0, strong0, full0, weak0 3 charge strengths: small, medium, large The use of x and z in defining the value of a number is case insensitive. x and z will be considered false in if expression. An x in hexadecimal shall be 4-bit unknown. An x in octal shall be 3-bit unknown. An x in binary shall be 1-bit unknown. The same as z case. ? is equivalent to z in literal number values.

Copyright © by Ando KiIntroduction to Verilog Basic ( 13 ) Verilog numbers (1/3) Verilog constant number can be specified as integer constant or real constant. Integer constants Decimal (123, 4d15) Hexadecimal (h12F, 4haBcD) Octal (o763, 3o7) Binary (b1010, 4b1100) Sized constant form: 4d15, 4hAbCd) Unsized constant form (123, h12F) Signed integer Negative numbers shall be represented in 2s complement format. Unsigned integer // Unsized constant numbers 659 // is a decimal number d659 'h837FF // is a hexadecimal number 'o7460 // is an octal number 4af // is illegal (hexadecimal format requires 'h) – 'h4af // Sized constant numbers 4'b1001 // is a 4-bit binary number 5'D3 // is a 5-bit decimal number 3'b01x // is a 3-bit number with the least significant bit unknown 12'hx // is a 12-bit unknown number 16'hz // is a 16-bit high-impedance number // Using sign with constant numbers 8'd-6 // this is illegal syntax -8'd6 // this defines the two's complement of 6, // held in 8 bits--equivalent to -(8'd 6) 4'shf // this denotes the 4-bit number '1111', to // be interpreted as a 2's complement number, // or '-1'. This is equivalent to -4'h1 -4'sd15 // this is equivalent to -(-4'd 1), or '0001' 16'sd? // the same as 16'sbz

Copyright © by Ando KiIntroduction to Verilog Basic ( 14 ) Verilog numbers (2/3) Integer constants An x shall be set 4-bit to unknown in the hexadecimal base, 3-bit in the octal base, and 1 bit in the binary base. Similarly, a z shall set 4, 3 and 1, respectively, to the high-impedance value. The underscore (_) shall be legal anywhere in a number except as the first character. Sized negative constant numbers and sized constant numbers are sign- extended when assigned to a reg data type, regardless of whether the reg itself is signed or not. // Automatic left padding reg [11:0] a, b, c, d; initial begin a = 'h x; // yields xxx b = 'h 3x; // yields 03x c = 'h z3; // yields zz3 d = 'h 0z3; // yields 0z3 end reg [84:0] e, f, g; e = 'h5; // yields {82{1'b0},3'b101} f = 'hx; // yields {85{1'hx}} g = 'hz; // yields {85{1'hz}} // Using underscore character in numbers 27_195_000 16'b0011_0101_0001_ 'h12ab_f001

Copyright © by Ando KiIntroduction to Verilog Basic ( 15 ) Verilog numbers (3/3) Real constants Decimal notation Scientific notation Real number and real variable are prohibited in the following cases. Edge description (posedge, negedge) Bit-select or part-select reference Index expression of bit-select or part-select Real to integer conversion Real number shall be converted to integer by rounding the real number to the nearest integer, rather than by truncating E12 (the exponent symbol can be e or E) 1.30e-2 0.1e-0 23E10 29E _763_e-12 (underscores are ignored) // illegal E3.2e-7 // conversion integer A; A = 35.7 // A will be 36 A = 35.5 // A will be 36 A = -1.5 // A will be -2 A = 1.5 // A will be 2

Copyright © by Ando KiIntroduction to Verilog Basic ( 16 ) Verilog constant number (1/2) number ::= decimal_number | octal_number | binary_number | hex_number | real_number decimal_number ::= [ sign ] unsigned_number | [ size ] decimal_base unsigned_number binary_number ::= [ size ] binary_base binary_digit { _ | binary_digit } octal_number ::= [ size ] octal_base octal_digit { _ | octal_digit } hex_number ::= [ size ] hex_base hex_digit { _ | hex_digit } real_number ::= [ sign ] unsigned_number. unsigned_number | [ sign ] unsigned_number [. unsigned_number ] e [ sign ] unsigned_number | [ sign ] unsigned_number [. unsigned_number ] E [ sign ] unsigned_number sign ::= + | - size ::= unsigned_number unsigned_number ::= decimal_digit { _ | decimal_digit } decimal_base ::= [s|S]d | [s|S]D binary_base ::= [s|S]b | [s|S]B octal_base ::= [s|S]o | [s|S]O hex_base ::= [s|S]h | [s|S]H decimal_digit ::= 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 binary_digit ::= x | X | z | Z | 0 | 1 octal_digit ::= x | X | z | Z | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 hex_digit ::= x | X | z | Z | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | a | b | c | d | e | f | A | B | C | D | E | F Bold type characters are terminals. Use single quotation, not back-quotation mark. Underscore (_) can be used to enhance readability Note that this is not complete version. Only decimal digit can be come first

Copyright © by Ando KiIntroduction to Verilog Basic ( 17 ) Verilog constant number (2/2) 1b0 // a single bit, zero value `b0 // 32-bit, all zeros 32b0 // 32-bit, all zeros (32b0000_0000_0000_0000_0000_0000_0000_0000) 4ha // a 4-bit hexa (4b1010) 5h5 // a 5-bit hexa (5b0_0101) 4hz // a 4-bit high-impedance (4bZZZZ) 4h?ZZ? // the same as 4hz since ? is an alternate form of z. 4bx // a 4-bit, all unknown 4d9 // a 4-bit decimal 9 // a 32-bit number (32b0000_0000_0000_0000_0000_0000_0000_1001) A // an illegal number {10{1b1}} // replication case

Copyright © by Ando KiIntroduction to Verilog Basic ( 18 ) Operators (1/2) Logical operators: &&, ||, ! Result in one bit value Bitwise operators (infix): &, |, ~, ^, ~^, ^~ Operation on bit by bit basis Reduction operators (prefix): &, |, ^, ~&, ~|, ~^, ^~ Result in one bit value Shift operators: >>, << Result in the same size, always fills zero Any X/x or Z/z will result in all X operatoroperation &&Logical and ||Logical or !Logical not operatoroperation &bitwise and |bitwise or ~bitwise not ^bitwise xor ~^ or ^~bitwise xnor operatoroperation &and |or ^xor ~&nand ~|nor ~^ or ^~xnor operatoroperation >>Shift right <<Shift left

Copyright © by Ando KiIntroduction to Verilog Basic ( 19 ) Operators (2/2) Concatenation operators: {, } Replication: {n{X}} Relational operators: >, =, <= Result in one bit value Logical equality operators: ==, != Result in either true or false Any X/x or Z/z results in X Case equality operators: ===, !== Exact match including X/x and Z/z Conditional operators: ? : Like 2-to-1 mux Arithmetic/math operators: +, -, *, /, % If any operand is x the result is x. Unary: +, - reg [7:0] a; reg [3:0] b, c; a = {b, c}; a = b; a = {4{1b1},c}; a = {5{2b01}; // 10b

Copyright © by Ando KiIntroduction to Verilog Basic ( 20 ) Forms of negation and AND/OR NegationAND/OR reg [3:0] a, b, c; a = 5; b = 0; c = 0; b = !a; // logical negation: b will be 4b0 c = ~a; // bit-wise negation: c will be 4b1010 reg [3:0] a, b, c, d; a = 4b1000 & 4b0001; // a will be 4b0 b = 4b1000 && 4b0001; // b will be 4b0001 c = 4b1000 | 4b0001; // c will be 4b1001 d = 4b1000 || 4b0001; // d will be 4b0001

Copyright © by Ando KiIntroduction to Verilog Basic ( 21 ) String A string is a sequence of character enclosed by double quotes () and contained on a single line. One character is represented by one 8- bit ASCII value. A string can be an unsigned integer constant represented by a sequence of 8-bit ASCII values. The contents on the left are padded with 0 when variable width is wider than required. The leftmost characters will be lost when variable width is narrower than required. // string variable declaration reg [8*12:1] stringvar; // 8*12 or 96-bit wide initial begin stringvar="Helloworld!"; end // string manipulation module string_test; reg [8*14:1] stringvar; reg [8*5:1] shortvar; initial begin stringvar = "Hello world"; $display("%s is stored as %h", stringvar,stringvar); stringvar = {stringvar,"!!!"}; $display("%s is stored as %h", stringvar,stringvar); shortvar = "Hello world"; $display("%s is stored as %h", shortvar,shortvar); end endmodule // the output Hello world is stored as c6c6f20776f726c64 Hello world!!! is stored as 48656c6c6f20776f726c world is stored as 776f726c64

Copyright © by Ando KiIntroduction to Verilog Basic ( 22 ) String example module top; reg [8*14:1] stringvar; reg [8*5:1] shortvar; initial begin stringvar = "Hello world"; $display("%s is stored as %h", stringvar,stringvar); stringvar = {stringvar,"!!!"}; $display("%s is stored as %h", stringvar,stringvar); shortvar = "Hello world"; $display("%s is stored as %h", shortvar,shortvar); end endmodule code/verilog/basic/string example. DIY

Copyright © by Ando KiIntroduction to Verilog Basic ( 23 ) Compiler directives Compiler directive or preprocessor directive `define `undef `include `ifdef, `else, and `endif `ifndef, `elsif `timescale

Copyright © by Ando KiIntroduction to Verilog Basic ( 24 ) define and undef define The directive `define creates a macro for text substitution. Once a text macro name is defined, it can be used anywhere in a source description. Redefinition of a text macro is allowed and the latest definition of a particular macro read by the compiler prevails when the macro name is encountered in the source text. `undef The directive `undef is used to undefine a previously defined text macro. `define SEL_A4b0000 `define SEL_B4b0001 `define FILE_Xmy_file.txt `undef SEL_A `undef SEL_B `undef FILE_X Use back-quotation, not single quotation mark

Copyright © by Ando KiIntroduction to Verilog Basic ( 25 ) `include The `include compiler directive allows one to include the contents of a source file in another file during compilation. The file name in the `include directive can be a full or relative path name. A file included in the source using the `include compiler directive may contain other `include compiler directives. The `include construct cannot be used recursively. Implementations may limit the maximum number of levels to which include files can be nested. `include my_file.v Use back-quotation, not single quotation mark

Copyright © by Ando KiIntroduction to Verilog Basic ( 26 ) `ifdef, `ifndef, `else, `elsif and `endif `ifdef - `elsif - `else - `endif The `ifdef compiler directive checks for the definition of a macro. If the macro is defined, then the line following the `ifdef directive are included. If the macro is not defined and an `else directive exists, then the source is compiled. `ifndef - `elsif - `else - `endif The `ifndef compiler directive checks for the definition of a macro. If the macro is not defined, then the line following the `ifndef directive are included. If the macro is defined and an `else directive exists, then the source is compiled. `ifdef CERTAIN_MACRO `include my_first.v `elsif ANOTHER_MACRO // bla bla.. `else `include my_second.v `endif `ifndef CERTAIN_MACRO `include my_first.v `elsif ANOTHER_MACRO // bla bla.. `else `include my_second.v `endif

Copyright © by Ando KiIntroduction to Verilog Basic ( 27 ) `timescale It specifies the time unit and time precision of the modules. It specifies the unit of measurement for time and delay values. It specifies the degree of accuracy for delays. Any time calculations would be internally rounded to the nearest the time precision. Its effect spans to all modules that follow this directive until another `timescale directive is read. timescale_compiler_directive ::= `timescale time_unit / time_precision `timescale 1 ns / 1 ps module xx (yy, zz); …… endmodule Char. string unitremarks sSecond- ms10 -3 secondMilli us10 -6 secondMicro ns10 -9 secondNano ps secondPico fs secondFemto Use back-quotation mark.

Copyright © by Ando KiIntroduction to Verilog Basic ( 28 ) Time scale example The `timescale 10 ns / 1 ns compiler directive specifies that the time unit for module test is 10 ns. As a result, the time values in the module are multiples of 10 ns, rounded to the nearest 1 ns; therefore, the value stored in parameter d is scaled to a delay of 16 ns. The value of parameter d is rounded from 1.55 to 1.6 according to the time precision. `timescale 10 ns / 1 ns module top; integer set; parameter d = 1.55; initial begin set = 0; #d set = 1; // 1.55*10 --> > 16 #d set = 2; // *10 --> > 32 #d set = 3; // *10 --> > 48 #d set = 4; // *10 --> > 64 end initial begin $dumpfile("wave.vcd"); $dumpvars(1); end endmodule DIY code/verilog/basic/timescale example.

Copyright © by Ando KiIntroduction to Verilog Basic ( 29 ) Verilog data types Verilog data type is designed to represent the data storage and transmission elements found in the digital hardware. Verilog data types Net wire Variable Reg Integer Real Time Realtime

Copyright © by Ando KiIntroduction to Verilog Basic ( 30 ) Nets (1/2) Represents a hardware wire Driven by logic Equal z (high-impedance) when unconnected Initial value is x (unknown) Should be used with continuous assignment to assign value, not procedural assignment Types of nets wire, wand, wor tri, tri0, tri1, triand, trior, trireg supply0 – global net GND supply1 – global net VCC (VDD) Types wireJust wireOnly one driver is allowed wandWired-ANDMultiple-driver worWired-ORMultiple-driver triTri-stateThe same as wire, but 3 states

Copyright © by Ando KiIntroduction to Verilog Basic ( 31 ) Nets (2/2) A B Y wire Y; // declaration assign Y = A & B; B A Y wand Y; // declaration assign Y = A; assign Y = B; wor Y; // declaration assign Y = A; assign Y = B; AY dr tri Y; // declaration assign Y = (dr) ? A : z; z or Z means high-impedance.

Copyright © by Ando KiIntroduction to Verilog Basic ( 32 ) Signal resolution

Copyright © by Ando KiIntroduction to Verilog Basic ( 33 ) Register, integer, real, and time Register Variable that stores unsigned value Can be a register (value holding unit) in real hardware Only one type: reg Can be signed by reg signed Variable that stores signed value Need initialization if needed, since not initialized automatically. Only one type: integer Normally 32-bit Real that stores signed floating point value Initialized to 0.0 automatically. Only one type: real Time is a special data type for simulation time Only one type: time Normally 64-bit `realtime stores time values as real number // declaration reg my_scalar_regA; reg my_scalar_regB; reg [7:0] my_vector_reg; // use inside procedure (initial or always block) my_scalar_regA = 1; my_scalar_regB = my_scalar_regA; my_vector_reg = 8hFA; // declaration integer my_int; real my_real; time my_time; // use inside procedure my_int = ; my_real = -3.99; my_time = $time; // get current sim. time

Copyright © by Ando KiIntroduction to Verilog Basic ( 34 ) Data type interpretation Data type interpretation by arithmetic operators Net, reg or time shall be treated as unsigned value by default. Integer, real or realtime shall be treated as signed value by default. Data typeInterpretation netUnsigned regUnsigned integerSigned, 2s complement timeUnsigned realSigned, floating point

Copyright © by Ando KiIntroduction to Verilog Basic ( 35 ) Assignments The assignment is the basic mechanism for placing values into nets and variables. The continuous assignment It assigns values to nets. It occurs whenever the value of the right- hand side changes. The procedural assignment It assigns values to variables. It occurs within procedures, such as always, initial, task, and function. wire wire_tmp1; assign wire_tmp1 = my_value; wire wire_tmp2 = my_value; Statement typeLeft-hand side (LHS) ContinuousNet (wire) ProcedureVariable (reg, integer, or time variable) wire [3:0] w; reg [3:0] a, b, c, d; initial a = 4h4; (c) b = c; (w) d = w; module full_adder(sum,cout,in1,in2,cin,clk,resetb); output sum, cout; input in1, in2, cin; input clk, resetb; wire sum, cout; reg rin1, rin2, rcin; wire s1, c1; wire s2, c2; (posedge clk or negedge resetb) begin if (resetb==1'b0) begin rin1 <= 1'b0; rin2 <= 1'b0; rcin <= 1'b0; end else begin rin1 <= in1; rin2 <= in2; rcin <= cin; end half_adder_gate ha1 (.S(s1),.C(c1),.A(rin1),.B(rin2)); half_adder_rtl ha2 (.S(s2),.C(c2),.A(s1),.B(rcin)); assign sum = s2; assign cout = c1|c2; endmodule Continuous assignment Procedural assignment

Copyright © by Ando KiIntroduction to Verilog Basic ( 36 ) Register assignment A register may be assigned value only within A procedural statement, i.e., statement within initial block or always block A user-defined sequential primitive A task A function A register may never be assigned value by A primitive gate output A continuous assignment wire wire_tmp1, wire_tmp2; reg reg_tmp; and Uand(reg_tmp, wire_tmp1, wire_tmp2); // illegal assign reg_tmp = wire_tmp1 & wire_tmp2; // illegal

Copyright © by Ando KiIntroduction to Verilog Basic ( 37 ) Vector and array data type Vector represents bus Left number is MS bit Vector assignment by position Array is a collection of the same data type // vectors wire [3:0] busA; // busA[3] is MSB reg [1:4] busB; // busB[1] is MSB reg [1:0] busC; // subfield access and positional assignment busC = busA[2:1]; // busC[1] = busA[2]; // busC[0] = busA[1]; // array integer my_int[1:5]; // 5 integer variables reg my_reg[0:99]; reg [7:0] my_mem[0:9]; reg my_x[7:0][0:10]; my_mem: 8-bit memory from address 0 to 9. my_x: two-dimensional one-bit register.

Copyright © by Ando KiIntroduction to Verilog Basic ( 38 ) Array declaration and assignments Array declarations Assignment to array elements reg [7:0] mema[0:255]; // declares a memory mema of bit registers. The indices are 0 to 255 reg arrayb[7:0][0:255]; // declare a two-dimensional array of one bit registers wire w_array[7:0][5:0]; // declare array of wires integer inta[1:64]; // an array of 64 integer values time chng_hist[1:1000] // an array of 1000 time values integer t_index; mema = 0; // Illegal syntax- Attempt to write to entire array arrayb[1] = 0; // Illegal Syntax - Attempt to write to elements [1][0]..[1][255] arrayb[1][12:31] = 0; // Illegal Syntax - Attempt to write to elements [1][12]..[1][31] mema[1] = 0; // Assigns 0 to the second element of mema arrayb[1][0] = 0; // Assigns 0 to the bit referenced by indices [1][0] inta[4] = 33559; // Assign decimal number to integer in array chng_hist[t_index] = $time; // Assign current simulation time to element addressed by integer index