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Презентация была опубликована год назад пользователемАнфиса Бирюкова

1 Logic and Computer Design Fundamentals Chapter 7 Registers and Counters

2 Chapter 7 - Part 1 2 Registers Register – a collection of binary storage elements In theory, a register is sequential logic which can be defined by a state table More often, think of a register as storing a vector of binary values Frequently used to perform simple data storage and data movement and processing operations

3 Chapter 7 - Part 1 3 How many states are there? How many input combinations? Output combinations? What is the output function? What is the next state function? Moore or Mealy? What are the quantities above for an n-bit register? Example: 2-bit Register C D Q C D Q CP In0 In1 A1 A0 Y1 Y0

4 Chapter 7 - Part 1 4 Register Design Models Due to the large numbers of states and input combinations as n becomes large, the state diagram/state table model is not feasible! What are methods we can use to design registers? Add predefined combinational circuits to registers Example: To count up, connect the register flip-flops to an incrementer Design individual cells using the state diagram/state table model and combine them into a register A 1-bit cell has just two states Output is usually the state variable

5 Chapter 7 - Part 1 5 Register Storage Expectations: A register can store information for multiple clock cycles To store or load information should be controlled by a signal Reality: A D flip-flop register loads information on every clock cycle Realizing expectations: Use a signal to block the clock to the register, Use a signal to control feedback of the output of the register back to its inputs, or Use other SR or JK flip-flops, that for (0,0) applied, store their state Load is a frequent name for the signal that controls register storage and loading Load = 1: Load the values on the data inputs Load = 0: Store the values in the register

6 Chapter 7 - Part 1 6 Registers with Clock Gating The Load signal enables the clock signal to pass through if 1 and prevents the clock signal from passing through if 0. Example: For Positive Edge-Triggered or Negative Pulse Master-Slave Flip-flop: What logic is needed for gating? What is the problem? Clock Load Gated Clock to FF Clock Skew of gated clocks with respect to clock or each other Gated Clock = Clock + Load

7 Chapter 7 - Part 1 7 A more reliable way to selectively load a register: Run the clock continuously, and Selectively use a load control to change the register contents. Example: 2-bit register with Load Control: For Load = 0, loads register contents (hold current values) For Load = 1, loads input values (load new values) Hardware more complex than clock gating, but free of timing problems Registers with Load-Controlled Feedback C D Q C D Q Clock In0 In1 A1 A0 Y1 Y0 Load 2-to-1 Multiplexers

8 Shift Registers Chapter 7 - Part 1 8 Capability to shift bits In one or both directions Why? Part of standard CPU instruction set Cheap multiplication/division Serial communications Just a chain of flip-flops

9 Chapter 7 - Part 1 9 Shift Registers Shift Registers move data laterally within the register toward its MSB or LSB position In the simplest case, the shift register is simply a set of D flip-flops connected in a row like this: Data input, In, is called a serial input or the shift right input. Data output, Out, is often called the serial output. The vector (A, B, C, Out) is called the parallel output.

10 Chapter 7 - Part 1 10 Shift Registers (continued) The behavior of the serial shift register is given in the listing on the lower right T0 is the register state just before the first clock pulse occurs T1 is after the first pulse and before the second. Initially unknown states are denoted by ? Complete the last three rows of the table DQDQDQDQ In Clock CP A B C Out

11 Chapter 7 - Part 1 11 Parallel Load Shift Registers By adding a mux between each shift register stage, data can be shifted or loaded If SHIFT is low, A and B are replaced by the data on D A and D B lines, else data shifts right on each clock. By adding more bits, we can make n-bit parallel load shift registers. A parallel load shift register with an added hold operation that stores data unchanged is given in Figure of the text. D Q D Q AB CP SHIFT IN DADA DBDB

12 Shift Register with Parallel Load Chapter 7 - Part 1 12

13 Chapter 7 - Part 1 13 By placing a 4-input multiplexer in front of each D flip- flop in a shift register, we can implement a circuit with shifts right, shifts left, parallel load, hold. Shift registers can also be designed to shift more than a single bit position right or left Shift registers can be designed to shift a variable number of bit positions specified by a variable called a shift amount. Shift Registers with Additional Functions

14 Shift Register with Parallel Load and Shift Direction Chapter 7 - Part 1 14

15 Basic Counters Chapter 7 - Part 1 15

16 Chapter 7 - Part 2 16 Counters are sequential circuits which "count" through a specific state sequence. They can count up, count down, or count through other fixed sequences. Two distinct types are in common usage: Ripple Counters Clock connected to the flip-flop clock input on the LSB bit flip- flop For all other bits, a flip-flop output is connected to the clock input, thus circuit is not truly synchronous! Output change is delayed more for each bit toward the MSB. Resurgent because of low power consumption Synchronous Counters Clock is directly connected to the flip-flop clock inputs Logic is used to implement the desired state sequencing Counters

17 Chapter 7 - Part 2 17 How does it work? When there is a positive edge on the clock input of A, A complements The clock input for flip- flop B is the complemented output of flip-flop A When flip A changes from 1 to 0, there is a positive edge on the clock input of B causing B to complement Reset Clock D D CRCR CRCR B A Ripple Counter CP B A

18 Chapter 7 - Part 2 18 The arrows show the cause-effect relation- ship from the prior slide => The corresponding sequence of states => (B,A) = (0,0), Each additional bit, C, D, …behaves like bit B, changing half as frequently as the bit before it. For 3 bits: (C,B,A) = (0,0,0), (0,0,1), (0,1,0), (0,1,1), (1,0,0), (1,0,1), (1,1,0), (1,1,1), (0,0,0), … Ripple Counter (continued) (1,0), (0,1), (0,1), … (0,0), (1,1), CP B A

19 Chapter 7 - Part 2 19 These circuits are called ripple counters because each edge sensitive transition (positive in the example) causes a change in the next flip-flops state. The changes ripple upward through the chain of flip-flops, i. e., each transition occurs after a clock-to-output delay from the stage before. To see this effect in detail look at the waveforms on the next slide. Ripple Counter (continued)

20 Chapter 7 - Part 2 20 Starting with C = B = A = 1, equivalent to (C,B,A) = 7 base 10, the next clock increments the count to (C,B,A) = 0 base 10. In fine timing detail: The clock to output delay t PHL causes an increasing delay from clock edge for each stage transition. Thus, the count ripples from least to most significant bit. For n bits, total worst case delay is n t PHL. Ripple Counter (continued) CP A B C t PHL t pHL

D3Q3 D2 Q2 D1 Q1 D0Q0 Clock I ncr e- " title="Chapter 7 - Part 2 21 Synchronous Counters To eliminate the "ripple" effects, use a common clock for each flip-flop and a combinational circuit to generate the next state. For an up-counter, use an incrementer => D3Q3 D2 Q2 D1 Q1 D0Q0 Clock I ncr e- " class="link_thumb"> 21 Chapter 7 - Part 2 21 Synchronous Counters To eliminate the "ripple" effects, use a common clock for each flip-flop and a combinational circuit to generate the next state. For an up-counter, use an incrementer => D3Q3 D2 Q2 D1 Q1 D0Q0 Clock I ncr e- menter A3 A2 A1 A0 S3 S2 S1 S0 D3Q3 D2 Q2 D1 Q1 D0Q0 Clock I ncr e- "> D3Q3 D2 Q2 D1 Q1 D0Q0 Clock I ncr e- menter A3 A2 A1 A0 S3 S2 S1 S0"> D3Q3 D2 Q2 D1 Q1 D0Q0 Clock I ncr e- " title="Chapter 7 - Part 2 21 Synchronous Counters To eliminate the "ripple" effects, use a common clock for each flip-flop and a combinational circuit to generate the next state. For an up-counter, use an incrementer => D3Q3 D2 Q2 D1 Q1 D0Q0 Clock I ncr e- ">

22 Chapter 7 - Part 2 22 Internal details => Internal Logic XOR complements each bit AND chain causes complement of a bit if all bits toward LSB from it equal 1 Count Enable Forces all outputs of AND chain to 0 to hold the state Carry Out Added as part of incrementer Connect to Count Enable of additional 4-bit counters to form larger counters Synchronous Counters (continued) Incrementer

23 23 Spring 2008 Arbitrary Count Counter goes through an arbitrary sequence Example: States 3 and 7 are not used

24 24 Spring 2008 State Diagram of Example Arbitrary Counter Analysis of state diagram shows: if circuit ever goes in an unused sate (011 or 111) the next clock transfers it to a valid state

25 25 Spring 2008 Circuit of Example Arbitrary Counter

26 Chapter 7 - Part 2 26 Design Example: Synchronous BCD Use the sequential logic model to design a synchronous BCD counter with D flip-flops State Table => Input combinations 1010 through 1111 are dont cares

27 Chapter 7 - Part 2 27 Synchronous BCD (continued) Use K-Maps to two-level optimize the next state equations and manipulate into forms containing XOR gates: D1 = Q1 D2 = Q2 + Q1Q8 D4 = Q4 + Q1Q2 D8 = Q8 + (Q1Q8 + Q1Q2Q4) The logic diagram can be draw from these equations An asynchronous or synchronous reset should be added What happens if the counter is perturbed by a power disturbance or other interference and it enters a state other than 0000 through 1001?

28 Chapter 7 - Part 2 28 For the BCD counter design, if an invalid state is entered, return to a valid state occurs within two clock cycles Is this adequate? If not: Is a signal needed that indicates that an invalid state has been entered? What is the equation for such a signal? Does the design need to be modified to return from an invalid state to a valid state in one clock cycle? Does the design need to be modified to return from a invalid state to a specific state (such as 0)? The action to be taken depends on: the application of the circuit design group policy See pages 244 of the text. Synchronous BCD (continued)

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